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authorThierry Reding <treding@nvidia.com>2014-12-19 09:19:21 -0500
committerThierry Reding <treding@nvidia.com>2015-01-27 04:14:56 -0500
commit3f0fb52ef013e76159b35386f22924f99d8034a4 (patch)
treed6378cbe5c1dc692c39b781463801ce84fdccf3e /drivers/gpu/drm/tegra/dsi.c
parent1503ca47d76e184eaeabe7cfa31de97b5ec36a04 (diff)
drm/tegra: Remove unused ->mode_fixup() callbacks
All output drivers have now been converted to use the ->atomic_check() callback, so the ->mode_fixup() callbacks are no longer used. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dsi.c')
-rw-r--r--drivers/gpu/drm/tegra/dsi.c87
1 files changed, 0 insertions, 87 deletions
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 00b307120cdd..6875885a2dca 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -786,92 +786,6 @@ static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
786{ 786{
787} 787}
788 788
789static bool tegra_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
790 const struct drm_display_mode *mode,
791 struct drm_display_mode *adjusted)
792{
793 struct tegra_output *output = encoder_to_output(encoder);
794 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
795 unsigned int mul, div, scdiv, vrefresh, lanes;
796 struct tegra_dsi *dsi = to_dsi(output);
797 struct mipi_dphy_timing timing;
798 unsigned long pclk, bclk, plld;
799 unsigned long period;
800 int err;
801
802 lanes = tegra_dsi_get_lanes(dsi);
803 pclk = mode->clock * 1000;
804
805 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
806 if (err < 0)
807 return err;
808
809 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, lanes);
810 vrefresh = drm_mode_vrefresh(mode);
811 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
812
813 /* compute byte clock */
814 bclk = (pclk * mul) / (div * lanes);
815
816 /*
817 * Compute bit clock and round up to the next MHz.
818 */
819 plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
820 period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
821
822 /*
823 * We divide the frequency by two here, but we make up for that by
824 * setting the shift clock divider (further below) to half of the
825 * correct value.
826 */
827 plld /= 2;
828
829 /*
830 * Derive pixel clock from bit clock using the shift clock divider.
831 * Note that this is only half of what we would expect, but we need
832 * that to make up for the fact that we divided the bit clock by a
833 * factor of two above.
834 *
835 * It's not clear exactly why this is necessary, but the display is
836 * not working properly otherwise. Perhaps the PLLs cannot generate
837 * frequencies sufficiently high.
838 */
839 scdiv = ((8 * mul) / (div * lanes)) - 2;
840
841 err = tegra_dc_setup_clock(dc, dsi->clk_parent, plld, scdiv);
842 if (err < 0) {
843 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
844 return false;
845 }
846
847 err = clk_set_rate(dsi->clk_parent, plld);
848 if (err < 0) {
849 dev_err(dsi->dev, "failed to set clock rate to %lu Hz\n",
850 plld);
851 return false;
852 }
853
854 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
855
856 err = mipi_dphy_timing_get_default(&timing, period);
857 if (err < 0)
858 return err;
859
860 err = mipi_dphy_timing_validate(&timing, period);
861 if (err < 0) {
862 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
863 return err;
864 }
865
866 /*
867 * The D-PHY timing fields are expressed in byte-clock cycles, so
868 * multiply the period by 8.
869 */
870 tegra_dsi_set_phy_timing(dsi, period * 8, &timing);
871
872 return true;
873}
874
875static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder) 789static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
876{ 790{
877} 791}
@@ -1053,7 +967,6 @@ tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1053 967
1054static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 968static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1055 .dpms = tegra_dsi_encoder_dpms, 969 .dpms = tegra_dsi_encoder_dpms,
1056 .mode_fixup = tegra_dsi_encoder_mode_fixup,
1057 .prepare = tegra_dsi_encoder_prepare, 970 .prepare = tegra_dsi_encoder_prepare,
1058 .commit = tegra_dsi_encoder_commit, 971 .commit = tegra_dsi_encoder_commit,
1059 .mode_set = tegra_dsi_encoder_mode_set, 972 .mode_set = tegra_dsi_encoder_mode_set,