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authorThierry Reding <treding@nvidia.com>2015-08-03 07:20:49 -0400
committerThierry Reding <treding@nvidia.com>2016-07-04 05:35:46 -0400
commit33a8eb8d40ee7fc07f23a407607bdbaa46893b2d (patch)
tree1a329f79c826febc5af299ef645801f85fb3a914 /drivers/gpu/drm/tegra/drm.c
parent2ccb396e9dd4536cfb7e8c4fd892d215c7aec2b6 (diff)
drm/tegra: dc: Implement runtime PM
Use runtime PM to clock-gate, assert reset and powergate the display controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. To make sure this works, make sure to only ever update planes on active CRTCs, otherwise register accesses to a clock-gated and reset CRTC will hang the CPU. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/drm.c')
-rw-r--r--drivers/gpu/drm/tegra/drm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index b59c3bf0df44..f753e239c55d 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -56,8 +56,8 @@ static void tegra_atomic_complete(struct tegra_drm *tegra,
56 */ 56 */
57 57
58 drm_atomic_helper_commit_modeset_disables(drm, state); 58 drm_atomic_helper_commit_modeset_disables(drm, state);
59 drm_atomic_helper_commit_planes(drm, state, false);
60 drm_atomic_helper_commit_modeset_enables(drm, state); 59 drm_atomic_helper_commit_modeset_enables(drm, state);
60 drm_atomic_helper_commit_planes(drm, state, true);
61 61
62 drm_atomic_helper_wait_for_vblanks(drm, state); 62 drm_atomic_helper_wait_for_vblanks(drm, state);
63 63