drm/radeon: consolidate UVD clock programming

Instead of duplicating the code over and over again, just use a single
function to handle the clock calculations.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 17 insertions, 93 deletions

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 91530d4c11c4..83f612a9500b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -44,56 +44,9 @@ void rv770_fini(struct radeon_device *rdev);
 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 
-static int rv770_uvd_calc_post_div(unsigned target_freq,
-                                   unsigned vco_freq,
-                                   unsigned *div)
-{
-        /* Fclk = Fvco / PDIV */
-        *div = vco_freq / target_freq;
-
-        /* we alway need a frequency less than or equal the target */
-        if ((vco_freq / *div) > target_freq)
-                *div += 1;
-
-        /* out of range ? */
-        if (*div > 30)
-                return -1; /* forget it */
-
-        *div -= 1;
-        return vco_freq / (*div + 1);
-}
-
-static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev)
-{
-        unsigned i;
-
-        /* assert UPLL_CTLREQ */
-        WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
-
-        /* wait for CTLACK and CTLACK2 to get asserted */
-        for (i = 0; i < 100; ++i) {
-                uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
-                if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
-                        break;
-                mdelay(10);
-        }
-        if (i == 100)
-                return -ETIMEDOUT;
-
-        /* deassert UPLL_CTLREQ */
-        WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
-
-        return 0;
-}
-
 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 {
-        /* start off with something large */
-        int optimal_diff_score = 0x7FFFFFF;
-        unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
-        unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
-        unsigned vco_freq, vco_min = 50000, vco_max = 160000;
-        unsigned ref_freq = rdev->clock.spll.reference_freq;
+        unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
         int r;
 
         /* RV740 uses evergreen uvd clk programming */
@@ -111,44 +64,15 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
                 return 0;
         }
 
-        /* loop through vco from low to high */
-        vco_min = max(max(vco_min, vclk), dclk);
-        for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
-                uint64_t fb_div = (uint64_t)vco_freq * 43663;
-                int calc_clk, diff_score, diff_vclk, diff_dclk;
-                unsigned vclk_div, dclk_div;
-
-                do_div(fb_div, ref_freq);
-                fb_div |= 1;
-
-                /* fb div out of range ? */
-                if (fb_div > 0x03FFFFFF)
-                        break; /* it can oly get worse */
-
-                /* calc vclk with current vco freq. */
-                calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
-                if (calc_clk == -1)
-                        break; /* vco is too big, it has to stop. */
-                diff_vclk = vclk - calc_clk;
-
-                /* calc dclk with current vco freq. */
-                calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
-                if (calc_clk == -1)
-                        break; /* vco is too big, it has to stop. */
-                diff_dclk = dclk - calc_clk;
-
-                /* determine if this vco setting is better than current optimal settings */
-                diff_score = abs(diff_vclk) + abs(diff_dclk);
-                if (diff_score < optimal_diff_score) {
-                        optimal_fb_div = fb_div;
-                        optimal_vclk_div = vclk_div;
-                        optimal_dclk_div = dclk_div;
-                        optimal_vco_freq = vco_freq;
-                        optimal_diff_score = diff_score;
-                        if (optimal_diff_score == 0)
-                                break; /* it can't get better than this */
-                }
-        }
+        r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
+                                          43663, 0x03FFFFFE, 1, 30, ~0,
+                                          &fb_div, &vclk_div, &dclk_div);
+        if (r)
+                return r;
+
+        fb_div |= 1;
+        vclk_div -= 1;
+        dclk_div -= 1;
 
         /* set UPLL_FB_DIV to 0x50000 */
         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
@@ -160,7 +84,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
 
-        r = rv770_uvd_send_upll_ctlreq(rdev);
+        r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
         if (r)
                 return r;
 
@@ -170,13 +94,13 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         /* set the required FB_DIV, REF_DIV, Post divder values */
         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
         WREG32_P(CG_UPLL_FUNC_CNTL_2,
-                 UPLL_SW_HILEN(optimal_vclk_div >> 1) |
-                 UPLL_SW_LOLEN((optimal_vclk_div >> 1) + (optimal_vclk_div & 1)) |
-                 UPLL_SW_HILEN2(optimal_dclk_div >> 1) |
-                 UPLL_SW_LOLEN2((optimal_dclk_div >> 1) + (optimal_dclk_div & 1)),
+                 UPLL_SW_HILEN(vclk_div >> 1) |
+                 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
+                 UPLL_SW_HILEN2(dclk_div >> 1) |
+                 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
                  ~UPLL_SW_MASK);
 
-        WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div),
+        WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
                  ~UPLL_FB_DIV_MASK);
 
         /* give the PLL some time to settle */
@@ -191,7 +115,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
         WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
 
-        r = rv770_uvd_send_upll_ctlreq(rdev);
+        r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
         if (r)
                 return r;