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authorChristian König <deathsimple@vodafone.de>2011-10-23 06:56:27 -0400
committerDave Airlie <airlied@redhat.com>2011-12-20 14:50:56 -0500
commite32eb50dbe43862606a51caa94368ec6bd019434 (patch)
treea064cf4e60c0d42694e5dcc3759794b4b24b8e77 /drivers/gpu/drm/radeon/rv515.c
parentd6d2730c71a5d41a121a7b567bf7ff9c5d4cd3ab (diff)
drm/radeon: rename struct radeon_cp to radeon_ring
That naming seems to make more sense, since we not only want to run PM4 rings with it. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515.c')
-rw-r--r--drivers/gpu/drm/radeon/rv515.c82
1 files changed, 41 insertions, 41 deletions
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 8a935987d022..beed57c7df96 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -55,45 +55,45 @@ void rv515_debugfs(struct radeon_device *rdev)
55 55
56void rv515_ring_start(struct radeon_device *rdev) 56void rv515_ring_start(struct radeon_device *rdev)
57{ 57{
58 struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]; 58 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
59 int r; 59 int r;
60 60
61 r = radeon_ring_lock(rdev, cp, 64); 61 r = radeon_ring_lock(rdev, ring, 64);
62 if (r) { 62 if (r) {
63 return; 63 return;
64 } 64 }
65 radeon_ring_write(cp, PACKET0(ISYNC_CNTL, 0)); 65 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
66 radeon_ring_write(cp, 66 radeon_ring_write(ring,
67 ISYNC_ANY2D_IDLE3D | 67 ISYNC_ANY2D_IDLE3D |
68 ISYNC_ANY3D_IDLE2D | 68 ISYNC_ANY3D_IDLE2D |
69 ISYNC_WAIT_IDLEGUI | 69 ISYNC_WAIT_IDLEGUI |
70 ISYNC_CPSCRATCH_IDLEGUI); 70 ISYNC_CPSCRATCH_IDLEGUI);
71 radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0)); 71 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
72 radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 72 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
73 radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0)); 73 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
74 radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG); 74 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
75 radeon_ring_write(cp, PACKET0(GB_SELECT, 0)); 75 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
76 radeon_ring_write(cp, 0); 76 radeon_ring_write(ring, 0);
77 radeon_ring_write(cp, PACKET0(GB_ENABLE, 0)); 77 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
78 radeon_ring_write(cp, 0); 78 radeon_ring_write(ring, 0);
79 radeon_ring_write(cp, PACKET0(R500_SU_REG_DEST, 0)); 79 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
80 radeon_ring_write(cp, (1 << rdev->num_gb_pipes) - 1); 80 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
81 radeon_ring_write(cp, PACKET0(VAP_INDEX_OFFSET, 0)); 81 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
82 radeon_ring_write(cp, 0); 82 radeon_ring_write(ring, 0);
83 radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 83 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
84 radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE); 84 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
85 radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 85 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
86 radeon_ring_write(cp, ZC_FLUSH | ZC_FREE); 86 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
87 radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0)); 87 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
88 radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 88 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
89 radeon_ring_write(cp, PACKET0(GB_AA_CONFIG, 0)); 89 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
90 radeon_ring_write(cp, 0); 90 radeon_ring_write(ring, 0);
91 radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 91 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
92 radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE); 92 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
93 radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 93 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
94 radeon_ring_write(cp, ZC_FLUSH | ZC_FREE); 94 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
95 radeon_ring_write(cp, PACKET0(GB_MSPOS0, 0)); 95 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
96 radeon_ring_write(cp, 96 radeon_ring_write(ring,
97 ((6 << MS_X0_SHIFT) | 97 ((6 << MS_X0_SHIFT) |
98 (6 << MS_Y0_SHIFT) | 98 (6 << MS_Y0_SHIFT) |
99 (6 << MS_X1_SHIFT) | 99 (6 << MS_X1_SHIFT) |
@@ -102,8 +102,8 @@ void rv515_ring_start(struct radeon_device *rdev)
102 (6 << MS_Y2_SHIFT) | 102 (6 << MS_Y2_SHIFT) |
103 (6 << MSBD0_Y_SHIFT) | 103 (6 << MSBD0_Y_SHIFT) |
104 (6 << MSBD0_X_SHIFT))); 104 (6 << MSBD0_X_SHIFT)));
105 radeon_ring_write(cp, PACKET0(GB_MSPOS1, 0)); 105 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
106 radeon_ring_write(cp, 106 radeon_ring_write(ring,
107 ((6 << MS_X3_SHIFT) | 107 ((6 << MS_X3_SHIFT) |
108 (6 << MS_Y3_SHIFT) | 108 (6 << MS_Y3_SHIFT) |
109 (6 << MS_X4_SHIFT) | 109 (6 << MS_X4_SHIFT) |
@@ -111,15 +111,15 @@ void rv515_ring_start(struct radeon_device *rdev)
111 (6 << MS_X5_SHIFT) | 111 (6 << MS_X5_SHIFT) |
112 (6 << MS_Y5_SHIFT) | 112 (6 << MS_Y5_SHIFT) |
113 (6 << MSBD1_SHIFT))); 113 (6 << MSBD1_SHIFT)));
114 radeon_ring_write(cp, PACKET0(GA_ENHANCE, 0)); 114 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
115 radeon_ring_write(cp, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 115 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
116 radeon_ring_write(cp, PACKET0(GA_POLY_MODE, 0)); 116 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
117 radeon_ring_write(cp, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 117 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
118 radeon_ring_write(cp, PACKET0(GA_ROUND_MODE, 0)); 118 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
119 radeon_ring_write(cp, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 119 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
120 radeon_ring_write(cp, PACKET0(0x20C8, 0)); 120 radeon_ring_write(ring, PACKET0(0x20C8, 0));
121 radeon_ring_write(cp, 0); 121 radeon_ring_write(ring, 0);
122 radeon_ring_unlock_commit(rdev, cp); 122 radeon_ring_unlock_commit(rdev, ring);
123} 123}
124 124
125int rv515_mc_wait_for_idle(struct radeon_device *rdev) 125int rv515_mc_wait_for_idle(struct radeon_device *rdev)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 03:35:51 -0500