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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-16 13:30:17 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-16 13:30:17 -0500 |
commit | c5113e3d66d7c7140fe854c7638a27eb3a23fd7d (patch) | |
tree | 9247edfcfa87132e15a277d6f2359b303c24da29 /drivers/gpu/drm/radeon/r300.c | |
parent | 9b2831704e9250269032e3b8c2ffdfca09fd2851 (diff) | |
parent | d785d78bbdb53580b12c40e820af5a3281ce2fc8 (diff) |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/radeon/kms: fix r100->r500 CS checker for compressed textures. (v2)
drm/radeon/kms: allow for texture tiling
drm/radeon/kms: init pm on all chipsets
drm/radeon/kms: HDMI support for R600 KMS
drm/radeon/kms: make sure mc is initialized before mapping blit bo
drm/radeon/kms: Return to userspace on ERESTARTSYS
drm/radeon/gem: don't leak a gem object if reserve fails on get tiling (v2)
drm/radeon/kms: don't report allocate failure on ERESTARTSYS
drm/radeon/kms: Check if bo we got from ttm are radeon object or not
drm/radeon/kms: If no placement is supplied fallback to system
drm/ttm: Fix memory type manager debug information printing
drm/ttm: Fix printk format & compute bo->mem.size at bo initialization
drm/ttm: Fix potential ttm_mem_evict_first races.
drm/ttm: Delayed delete fixes.
drm/ttm: fix two bugs in new placement routines.
drm/ttm: fix incorrect logic in ttm_bo_io path
drm/nouveau: remove use of -ERESTART
nouveau: Fix endianness with new context program loader
drm/nouveau: fix build with CONFIG_AGP=n
drm/nouveau: fix ch7006 build
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 83378c39d0e3..83490c2b5061 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -686,7 +686,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
686 | r100_cs_dump_packet(p, pkt); | 686 | r100_cs_dump_packet(p, pkt); |
687 | return r; | 687 | return r; |
688 | } | 688 | } |
689 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | 689 | |
690 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | ||
691 | tile_flags |= R300_TXO_MACRO_TILE; | ||
692 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | ||
693 | tile_flags |= R300_TXO_MICRO_TILE; | ||
694 | |||
695 | tmp = idx_value + ((u32)reloc->lobj.gpu_offset); | ||
696 | tmp |= tile_flags; | ||
697 | ib[idx] = tmp; | ||
690 | track->textures[i].robj = reloc->robj; | 698 | track->textures[i].robj = reloc->robj; |
691 | break; | 699 | break; |
692 | /* Tracked registers */ | 700 | /* Tracked registers */ |
@@ -852,7 +860,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
852 | case R300_TX_FORMAT_Z6Y5X5: | 860 | case R300_TX_FORMAT_Z6Y5X5: |
853 | case R300_TX_FORMAT_W4Z4Y4X4: | 861 | case R300_TX_FORMAT_W4Z4Y4X4: |
854 | case R300_TX_FORMAT_W1Z5Y5X5: | 862 | case R300_TX_FORMAT_W1Z5Y5X5: |
855 | case R300_TX_FORMAT_DXT1: | ||
856 | case R300_TX_FORMAT_D3DMFT_CxV8U8: | 863 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
857 | case R300_TX_FORMAT_B8G8_B8G8: | 864 | case R300_TX_FORMAT_B8G8_B8G8: |
858 | case R300_TX_FORMAT_G8R8_G8B8: | 865 | case R300_TX_FORMAT_G8R8_G8B8: |
@@ -866,8 +873,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
866 | case 0x17: | 873 | case 0x17: |
867 | case R300_TX_FORMAT_FL_I32: | 874 | case R300_TX_FORMAT_FL_I32: |
868 | case 0x1e: | 875 | case 0x1e: |
869 | case R300_TX_FORMAT_DXT3: | ||
870 | case R300_TX_FORMAT_DXT5: | ||
871 | track->textures[i].cpp = 4; | 876 | track->textures[i].cpp = 4; |
872 | break; | 877 | break; |
873 | case R300_TX_FORMAT_W16Z16Y16X16: | 878 | case R300_TX_FORMAT_W16Z16Y16X16: |
@@ -878,6 +883,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
878 | case R300_TX_FORMAT_FL_R32G32B32A32: | 883 | case R300_TX_FORMAT_FL_R32G32B32A32: |
879 | track->textures[i].cpp = 16; | 884 | track->textures[i].cpp = 16; |
880 | break; | 885 | break; |
886 | case R300_TX_FORMAT_DXT1: | ||
887 | track->textures[i].cpp = 1; | ||
888 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | ||
889 | break; | ||
890 | case R300_TX_FORMAT_DXT3: | ||
891 | case R300_TX_FORMAT_DXT5: | ||
892 | track->textures[i].cpp = 1; | ||
893 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | ||
894 | break; | ||
881 | default: | 895 | default: |
882 | DRM_ERROR("Invalid texture format %u\n", | 896 | DRM_ERROR("Invalid texture format %u\n", |
883 | (idx_value & 0x1F)); | 897 | (idx_value & 0x1F)); |
@@ -1324,6 +1338,8 @@ int r300_init(struct radeon_device *rdev) | |||
1324 | r300_errata(rdev); | 1338 | r300_errata(rdev); |
1325 | /* Initialize clocks */ | 1339 | /* Initialize clocks */ |
1326 | radeon_get_clock_info(rdev->ddev); | 1340 | radeon_get_clock_info(rdev->ddev); |
1341 | /* Initialize power management */ | ||
1342 | radeon_pm_init(rdev); | ||
1327 | /* Get vram informations */ | 1343 | /* Get vram informations */ |
1328 | r300_vram_info(rdev); | 1344 | r300_vram_info(rdev); |
1329 | /* Initialize memory controller (also test AGP) */ | 1345 | /* Initialize memory controller (also test AGP) */ |