aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/ni.c
diff options
context:
space:
mode:
authorJerome Glisse <jglisse@redhat.com>2011-11-15 11:48:34 -0500
committerDave Airlie <airlied@redhat.com>2011-12-20 14:52:12 -0500
commitb15ba51207e54245409d6f46e20dab36f906eed1 (patch)
treeb34a37395efa5be0a9af4ba5b627e43813713ed3 /drivers/gpu/drm/radeon/ni.c
parent1b37078b7ddf35cab12ac6544187e3636d50c0dc (diff)
drm/radeon: introduce a sub allocator and convert ib pool to it v4
Somewhat specializaed sub-allocator designed to perform sub-allocation for command buffer not only for current cs ioctl but for future command submission ioctl as well. Patch also convert current ib pool to use the sub allocator. Idea is that ib poll buffer can be share with other command buffer submission not having 64K granularity. v2 Harmonize pool handling and add suspend/resume callback to pin/unpin sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman, rs480, rs690, rs880) v3 Simplify allocator v4 Fix radeon_ib_get error path to properly free fence Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c45
1 files changed, 22 insertions, 23 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 30562622b94a..d89b2ebd5bbb 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1453,6 +1453,17 @@ static int cayman_startup(struct radeon_device *rdev)
1453 if (r) 1453 if (r)
1454 return r; 1454 return r;
1455 1455
1456 r = radeon_ib_pool_start(rdev);
1457 if (r)
1458 return r;
1459
1460 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1461 if (r) {
1462 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1463 rdev->accel_working = false;
1464 return r;
1465 }
1466
1456 return 0; 1467 return 0;
1457} 1468}
1458 1469
@@ -1467,32 +1478,25 @@ int cayman_resume(struct radeon_device *rdev)
1467 /* post card */ 1478 /* post card */
1468 atom_asic_init(rdev->mode_info.atom_context); 1479 atom_asic_init(rdev->mode_info.atom_context);
1469 1480
1481 rdev->accel_working = true;
1470 r = cayman_startup(rdev); 1482 r = cayman_startup(rdev);
1471 if (r) { 1483 if (r) {
1472 DRM_ERROR("cayman startup failed on resume\n"); 1484 DRM_ERROR("cayman startup failed on resume\n");
1473 return r; 1485 return r;
1474 } 1486 }
1475
1476 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1477 if (r) {
1478 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1479 return r;
1480 }
1481
1482 return r; 1487 return r;
1483
1484} 1488}
1485 1489
1486int cayman_suspend(struct radeon_device *rdev) 1490int cayman_suspend(struct radeon_device *rdev)
1487{ 1491{
1488 /* FIXME: we should wait for ring to be empty */ 1492 /* FIXME: we should wait for ring to be empty */
1493 radeon_ib_pool_suspend(rdev);
1494 r600_blit_suspend(rdev);
1489 cayman_cp_enable(rdev, false); 1495 cayman_cp_enable(rdev, false);
1490 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1496 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1491 evergreen_irq_suspend(rdev); 1497 evergreen_irq_suspend(rdev);
1492 radeon_wb_disable(rdev); 1498 radeon_wb_disable(rdev);
1493 cayman_pcie_gart_disable(rdev); 1499 cayman_pcie_gart_disable(rdev);
1494 r600_blit_suspend(rdev);
1495
1496 return 0; 1500 return 0;
1497} 1501}
1498 1502
@@ -1567,29 +1571,24 @@ int cayman_init(struct radeon_device *rdev)
1567 if (r) 1571 if (r)
1568 return r; 1572 return r;
1569 1573
1574 r = radeon_ib_pool_init(rdev);
1570 rdev->accel_working = true; 1575 rdev->accel_working = true;
1576 if (r) {
1577 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1578 rdev->accel_working = false;
1579 }
1580
1571 r = cayman_startup(rdev); 1581 r = cayman_startup(rdev);
1572 if (r) { 1582 if (r) {
1573 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1583 dev_err(rdev->dev, "disabling GPU acceleration\n");
1574 cayman_cp_fini(rdev); 1584 cayman_cp_fini(rdev);
1575 r600_irq_fini(rdev); 1585 r600_irq_fini(rdev);
1576 radeon_wb_fini(rdev); 1586 radeon_wb_fini(rdev);
1587 r100_ib_fini(rdev);
1577 radeon_irq_kms_fini(rdev); 1588 radeon_irq_kms_fini(rdev);
1578 cayman_pcie_gart_fini(rdev); 1589 cayman_pcie_gart_fini(rdev);
1579 rdev->accel_working = false; 1590 rdev->accel_working = false;
1580 } 1591 }
1581 if (rdev->accel_working) {
1582 r = radeon_ib_pool_init(rdev);
1583 if (r) {
1584 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1585 rdev->accel_working = false;
1586 }
1587 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1588 if (r) {
1589 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1590 rdev->accel_working = false;
1591 }
1592 }
1593 1592
1594 /* Don't start up if the MC ucode is missing. 1593 /* Don't start up if the MC ucode is missing.
1595 * The default clocks and voltages before the MC ucode 1594 * The default clocks and voltages before the MC ucode
@@ -1609,7 +1608,7 @@ void cayman_fini(struct radeon_device *rdev)
1609 cayman_cp_fini(rdev); 1608 cayman_cp_fini(rdev);
1610 r600_irq_fini(rdev); 1609 r600_irq_fini(rdev);
1611 radeon_wb_fini(rdev); 1610 radeon_wb_fini(rdev);
1612 radeon_ib_pool_fini(rdev); 1611 r100_ib_fini(rdev);
1613 radeon_irq_kms_fini(rdev); 1612 radeon_irq_kms_fini(rdev);
1614 cayman_pcie_gart_fini(rdev); 1613 cayman_pcie_gart_fini(rdev);
1615 r600_vram_scratch_fini(rdev); 1614 r600_vram_scratch_fini(rdev);