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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2017-08-04 18:43:52 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2017-08-15 08:18:25 -0400
commitfecea2528d4e92db46eb11b23458ed56023301f2 (patch)
tree37cf851d6544f8ecab6ca7c21674fbaf84eaa679 /drivers/gpu/drm/omapdrm
parentcc219afa1853f230ac35f40e6ead5b143f9614b5 (diff)
drm: omapdrm: dss: Split operations out of dss_features structure
Move the two function pointers to a new dss_ops structure. This will allow merging the dss_features and omap_dss_features structures without having to expose the DPI source selection and LCD clock muxing functions in header files. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.c50
1 files changed, 35 insertions, 15 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index 99e22ca972c7..b8a2f92efcba 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -69,15 +69,19 @@ struct dss_reg {
69#define REG_FLD_MOD(idx, val, start, end) \ 69#define REG_FLD_MOD(idx, val, start, end) \
70 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 70 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
71 71
72struct dss_ops {
73 int (*dpi_select_source)(int port, enum omap_channel channel);
74 int (*select_lcd_source)(enum omap_channel channel,
75 enum dss_clk_source clk_src);
76};
77
72struct dss_features { 78struct dss_features {
73 u8 fck_div_max; 79 u8 fck_div_max;
74 u8 dss_fck_multiplier; 80 u8 dss_fck_multiplier;
75 const char *parent_clk_name; 81 const char *parent_clk_name;
76 const enum omap_display_type *ports; 82 const enum omap_display_type *ports;
77 int num_ports; 83 int num_ports;
78 int (*dpi_select_source)(int port, enum omap_channel channel); 84 const struct dss_ops *ops;
79 int (*select_lcd_source)(enum omap_channel channel,
80 enum dss_clk_source clk_src);
81}; 85};
82 86
83static struct { 87static struct {
@@ -576,7 +580,7 @@ void dss_select_lcd_clk_source(enum omap_channel channel,
576 return; 580 return;
577 } 581 }
578 582
579 r = dss.feat->select_lcd_source(channel, clk_src); 583 r = dss.feat->ops->select_lcd_source(channel, clk_src);
580 if (r) 584 if (r)
581 return; 585 return;
582 586
@@ -823,7 +827,7 @@ static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
823 827
824int dss_dpi_select_source(int port, enum omap_channel channel) 828int dss_dpi_select_source(int port, enum omap_channel channel)
825{ 829{
826 return dss.feat->dpi_select_source(port, channel); 830 return dss.feat->ops->dpi_select_source(port, channel);
827} 831}
828 832
829static int dss_get_clocks(void) 833static int dss_get_clocks(void)
@@ -893,6 +897,25 @@ void dss_debug_dump_clocks(struct seq_file *s)
893#endif 897#endif
894 898
895 899
900static const struct dss_ops dss_ops_omap2_omap3 = {
901 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
902};
903
904static const struct dss_ops dss_ops_omap4 = {
905 .dpi_select_source = &dss_dpi_select_source_omap4,
906 .select_lcd_source = &dss_lcd_clk_mux_omap4,
907};
908
909static const struct dss_ops dss_ops_omap5 = {
910 .dpi_select_source = &dss_dpi_select_source_omap5,
911 .select_lcd_source = &dss_lcd_clk_mux_omap5,
912};
913
914static const struct dss_ops dss_ops_dra7 = {
915 .dpi_select_source = &dss_dpi_select_source_dra7xx,
916 .select_lcd_source = &dss_lcd_clk_mux_dra7,
917};
918
896static const enum omap_display_type omap2plus_ports[] = { 919static const enum omap_display_type omap2plus_ports[] = {
897 OMAP_DISPLAY_TYPE_DPI, 920 OMAP_DISPLAY_TYPE_DPI,
898}; 921};
@@ -916,66 +939,63 @@ static const struct dss_features omap24xx_dss_feats = {
916 .fck_div_max = 6, 939 .fck_div_max = 6,
917 .dss_fck_multiplier = 2, 940 .dss_fck_multiplier = 2,
918 .parent_clk_name = "core_ck", 941 .parent_clk_name = "core_ck",
919 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
920 .ports = omap2plus_ports, 942 .ports = omap2plus_ports,
921 .num_ports = ARRAY_SIZE(omap2plus_ports), 943 .num_ports = ARRAY_SIZE(omap2plus_ports),
944 .ops = &dss_ops_omap2_omap3,
922}; 945};
923 946
924static const struct dss_features omap34xx_dss_feats = { 947static const struct dss_features omap34xx_dss_feats = {
925 .fck_div_max = 16, 948 .fck_div_max = 16,
926 .dss_fck_multiplier = 2, 949 .dss_fck_multiplier = 2,
927 .parent_clk_name = "dpll4_ck", 950 .parent_clk_name = "dpll4_ck",
928 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
929 .ports = omap34xx_ports, 951 .ports = omap34xx_ports,
930 .num_ports = ARRAY_SIZE(omap34xx_ports), 952 .num_ports = ARRAY_SIZE(omap34xx_ports),
953 .ops = &dss_ops_omap2_omap3,
931}; 954};
932 955
933static const struct dss_features omap3630_dss_feats = { 956static const struct dss_features omap3630_dss_feats = {
934 .fck_div_max = 32, 957 .fck_div_max = 32,
935 .dss_fck_multiplier = 1, 958 .dss_fck_multiplier = 1,
936 .parent_clk_name = "dpll4_ck", 959 .parent_clk_name = "dpll4_ck",
937 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
938 .ports = omap2plus_ports, 960 .ports = omap2plus_ports,
939 .num_ports = ARRAY_SIZE(omap2plus_ports), 961 .num_ports = ARRAY_SIZE(omap2plus_ports),
962 .ops = &dss_ops_omap2_omap3,
940}; 963};
941 964
942static const struct dss_features omap44xx_dss_feats = { 965static const struct dss_features omap44xx_dss_feats = {
943 .fck_div_max = 32, 966 .fck_div_max = 32,
944 .dss_fck_multiplier = 1, 967 .dss_fck_multiplier = 1,
945 .parent_clk_name = "dpll_per_x2_ck", 968 .parent_clk_name = "dpll_per_x2_ck",
946 .dpi_select_source = &dss_dpi_select_source_omap4,
947 .ports = omap2plus_ports, 969 .ports = omap2plus_ports,
948 .num_ports = ARRAY_SIZE(omap2plus_ports), 970 .num_ports = ARRAY_SIZE(omap2plus_ports),
949 .select_lcd_source = &dss_lcd_clk_mux_omap4, 971 .ops = &dss_ops_omap4,
950}; 972};
951 973
952static const struct dss_features omap54xx_dss_feats = { 974static const struct dss_features omap54xx_dss_feats = {
953 .fck_div_max = 64, 975 .fck_div_max = 64,
954 .dss_fck_multiplier = 1, 976 .dss_fck_multiplier = 1,
955 .parent_clk_name = "dpll_per_x2_ck", 977 .parent_clk_name = "dpll_per_x2_ck",
956 .dpi_select_source = &dss_dpi_select_source_omap5,
957 .ports = omap2plus_ports, 978 .ports = omap2plus_ports,
958 .num_ports = ARRAY_SIZE(omap2plus_ports), 979 .num_ports = ARRAY_SIZE(omap2plus_ports),
959 .select_lcd_source = &dss_lcd_clk_mux_omap5, 980 .ops = &dss_ops_omap5,
960}; 981};
961 982
962static const struct dss_features am43xx_dss_feats = { 983static const struct dss_features am43xx_dss_feats = {
963 .fck_div_max = 0, 984 .fck_div_max = 0,
964 .dss_fck_multiplier = 0, 985 .dss_fck_multiplier = 0,
965 .parent_clk_name = NULL, 986 .parent_clk_name = NULL,
966 .dpi_select_source = &dss_dpi_select_source_omap2_omap3,
967 .ports = omap2plus_ports, 987 .ports = omap2plus_ports,
968 .num_ports = ARRAY_SIZE(omap2plus_ports), 988 .num_ports = ARRAY_SIZE(omap2plus_ports),
989 .ops = &dss_ops_omap2_omap3,
969}; 990};
970 991
971static const struct dss_features dra7xx_dss_feats = { 992static const struct dss_features dra7xx_dss_feats = {
972 .fck_div_max = 64, 993 .fck_div_max = 64,
973 .dss_fck_multiplier = 1, 994 .dss_fck_multiplier = 1,
974 .parent_clk_name = "dpll_per_x2_ck", 995 .parent_clk_name = "dpll_per_x2_ck",
975 .dpi_select_source = &dss_dpi_select_source_dra7xx,
976 .ports = dra7xx_ports, 996 .ports = dra7xx_ports,
977 .num_ports = ARRAY_SIZE(dra7xx_ports), 997 .num_ports = ARRAY_SIZE(dra7xx_ports),
978 .select_lcd_source = &dss_lcd_clk_mux_dra7, 998 .ops = &dss_ops_dra7,
979}; 999};
980 1000
981static int dss_init_features(struct platform_device *pdev) 1001static int dss_init_features(struct platform_device *pdev)