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authorJyri Sarha <jsarha@ti.com>2017-03-24 10:47:52 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2017-04-03 05:36:40 -0400
commit864050c78e1c5d619da3c1b0a891d474dfd336bf (patch)
tree4d7b95cc0c0e791853453cdf10162cef7475ab89 /drivers/gpu/drm/omapdrm
parentf1118b893e65ada7845c587f4682b153ea40e2ad (diff)
drm/omap: Rename enum omap_plane to enum omap_plane_id
The enum omap_plane conflicted with the same struct name for omapdrm plane private data. This rename should solve the conflict. The rename was implement with this very simple coccinelle patch: ------------------------ @@ @@ enum -omap_plane +omap_plane_id ------------------------ The patch was applied like this: spatch --sp-file <cocci_file> --all-includes --in-place --dir drivers/gpu/drm/omapdrm The above patch did not rename the actual enum definition. That was added manually on top of the spatch changes. Signed-off-by: Jyri Sarha <jsarha@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c124
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.h62
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.h5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss_features.c6
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss_features.h6
-rw-r--r--drivers/gpu/drm/omapdrm/dss/omapdss.h17
6 files changed, 117 insertions, 103 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 2e6a71dbc25d..8100fec2ca7b 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -303,8 +303,8 @@ static unsigned long dispc_core_clk_rate(void);
303static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 303static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
304static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 304static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
305 305
306static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); 306static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane);
307static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); 307static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane);
308 308
309static void dispc_clear_irqstatus(u32 mask); 309static void dispc_clear_irqstatus(u32 mask);
310static bool dispc_mgr_is_enabled(enum omap_channel channel); 310static bool dispc_mgr_is_enabled(enum omap_channel channel);
@@ -653,7 +653,7 @@ bool dispc_wb_go_busy(void)
653 653
654void dispc_wb_go(void) 654void dispc_wb_go(void)
655{ 655{
656 enum omap_plane plane = OMAP_DSS_WB; 656 enum omap_plane_id plane = OMAP_DSS_WB;
657 bool enable, go; 657 bool enable, go;
658 658
659 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 659 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
@@ -670,29 +670,33 @@ void dispc_wb_go(void)
670 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); 670 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
671} 671}
672 672
673static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) 673static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg,
674 u32 value)
674{ 675{
675 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 676 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
676} 677}
677 678
678static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) 679static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg,
680 u32 value)
679{ 681{
680 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 682 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
681} 683}
682 684
683static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) 685static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg,
686 u32 value)
684{ 687{
685 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 688 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
686} 689}
687 690
688static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) 691static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg,
692 u32 value)
689{ 693{
690 BUG_ON(plane == OMAP_DSS_GFX); 694 BUG_ON(plane == OMAP_DSS_GFX);
691 695
692 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 696 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
693} 697}
694 698
695static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, 699static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg,
696 u32 value) 700 u32 value)
697{ 701{
698 BUG_ON(plane == OMAP_DSS_GFX); 702 BUG_ON(plane == OMAP_DSS_GFX);
@@ -700,14 +704,15 @@ static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
700 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 704 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
701} 705}
702 706
703static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) 707static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg,
708 u32 value)
704{ 709{
705 BUG_ON(plane == OMAP_DSS_GFX); 710 BUG_ON(plane == OMAP_DSS_GFX);
706 711
707 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 712 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
708} 713}
709 714
710static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, 715static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
711 int fir_vinc, int five_taps, 716 int fir_vinc, int five_taps,
712 enum omap_color_component color_comp) 717 enum omap_color_component color_comp)
713{ 718{
@@ -753,7 +758,7 @@ static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
753} 758}
754 759
755 760
756static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, 761static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane,
757 const struct color_conv_coef *ct) 762 const struct color_conv_coef *ct)
758{ 763{
759#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 764#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
@@ -789,27 +794,27 @@ static void dispc_setup_color_conv_coef(void)
789 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 794 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
790} 795}
791 796
792static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) 797static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr)
793{ 798{
794 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 799 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
795} 800}
796 801
797static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) 802static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr)
798{ 803{
799 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 804 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
800} 805}
801 806
802static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) 807static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr)
803{ 808{
804 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 809 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
805} 810}
806 811
807static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) 812static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr)
808{ 813{
809 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 814 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
810} 815}
811 816
812static void dispc_ovl_set_pos(enum omap_plane plane, 817static void dispc_ovl_set_pos(enum omap_plane_id plane,
813 enum omap_overlay_caps caps, int x, int y) 818 enum omap_overlay_caps caps, int x, int y)
814{ 819{
815 u32 val; 820 u32 val;
@@ -822,7 +827,7 @@ static void dispc_ovl_set_pos(enum omap_plane plane,
822 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 827 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
823} 828}
824 829
825static void dispc_ovl_set_input_size(enum omap_plane plane, int width, 830static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width,
826 int height) 831 int height)
827{ 832{
828 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 833 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
@@ -833,7 +838,7 @@ static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
833 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 838 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
834} 839}
835 840
836static void dispc_ovl_set_output_size(enum omap_plane plane, int width, 841static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width,
837 int height) 842 int height)
838{ 843{
839 u32 val; 844 u32 val;
@@ -848,7 +853,7 @@ static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
848 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 853 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
849} 854}
850 855
851static void dispc_ovl_set_zorder(enum omap_plane plane, 856static void dispc_ovl_set_zorder(enum omap_plane_id plane,
852 enum omap_overlay_caps caps, u8 zorder) 857 enum omap_overlay_caps caps, u8 zorder)
853{ 858{
854 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 859 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
@@ -868,7 +873,7 @@ static void dispc_ovl_enable_zorder_planes(void)
868 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
869} 874}
870 875
871static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, 876static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane,
872 enum omap_overlay_caps caps, bool enable) 877 enum omap_overlay_caps caps, bool enable)
873{ 878{
874 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 879 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
@@ -877,7 +882,7 @@ static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
877 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 882 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
878} 883}
879 884
880static void dispc_ovl_setup_global_alpha(enum omap_plane plane, 885static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane,
881 enum omap_overlay_caps caps, u8 global_alpha) 886 enum omap_overlay_caps caps, u8 global_alpha)
882{ 887{
883 static const unsigned shifts[] = { 0, 8, 16, 24, }; 888 static const unsigned shifts[] = { 0, 8, 16, 24, };
@@ -890,17 +895,17 @@ static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
890 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 895 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
891} 896}
892 897
893static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) 898static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc)
894{ 899{
895 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 900 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
896} 901}
897 902
898static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) 903static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc)
899{ 904{
900 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 905 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
901} 906}
902 907
903static void dispc_ovl_set_color_mode(enum omap_plane plane, 908static void dispc_ovl_set_color_mode(enum omap_plane_id plane,
904 enum omap_color_mode color_mode) 909 enum omap_color_mode color_mode)
905{ 910{
906 u32 m = 0; 911 u32 m = 0;
@@ -981,7 +986,7 @@ static void dispc_ovl_set_color_mode(enum omap_plane plane,
981 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 986 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
982} 987}
983 988
984static void dispc_ovl_configure_burst_type(enum omap_plane plane, 989static void dispc_ovl_configure_burst_type(enum omap_plane_id plane,
985 enum omap_dss_rotation_type rotation_type) 990 enum omap_dss_rotation_type rotation_type)
986{ 991{
987 if (dss_has_feature(FEAT_BURST_2D) == 0) 992 if (dss_has_feature(FEAT_BURST_2D) == 0)
@@ -993,7 +998,8 @@ static void dispc_ovl_configure_burst_type(enum omap_plane plane,
993 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 998 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
994} 999}
995 1000
996static void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) 1001static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1002 enum omap_channel channel)
997{ 1003{
998 int shift; 1004 int shift;
999 u32 val; 1005 u32 val;
@@ -1054,7 +1060,7 @@ static void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel c
1054 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1060 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1055} 1061}
1056 1062
1057static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) 1063static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
1058{ 1064{
1059 int shift; 1065 int shift;
1060 u32 val; 1066 u32 val;
@@ -1096,12 +1102,12 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1096 1102
1097void dispc_wb_set_channel_in(enum dss_writeback_channel channel) 1103void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1098{ 1104{
1099 enum omap_plane plane = OMAP_DSS_WB; 1105 enum omap_plane_id plane = OMAP_DSS_WB;
1100 1106
1101 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); 1107 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1102} 1108}
1103 1109
1104static void dispc_ovl_set_burst_size(enum omap_plane plane, 1110static void dispc_ovl_set_burst_size(enum omap_plane_id plane,
1105 enum omap_burst_size burst_size) 1111 enum omap_burst_size burst_size)
1106{ 1112{
1107 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1113 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
@@ -1123,14 +1129,14 @@ static void dispc_configure_burst_sizes(void)
1123 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1129 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1124} 1130}
1125 1131
1126static u32 dispc_ovl_get_burst_size(enum omap_plane plane) 1132static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane)
1127{ 1133{
1128 unsigned unit = dss_feat_get_burst_size_unit(); 1134 unsigned unit = dss_feat_get_burst_size_unit();
1129 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1135 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1130 return unit * 8; 1136 return unit * 8;
1131} 1137}
1132 1138
1133static enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane plane) 1139static enum omap_color_mode dispc_ovl_get_color_modes(enum omap_plane_id plane)
1134{ 1140{
1135 return dss_feat_get_supported_color_modes(plane); 1141 return dss_feat_get_supported_color_modes(plane);
1136} 1142}
@@ -1168,7 +1174,8 @@ static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1168 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1174 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1169} 1175}
1170 1176
1171static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) 1177static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane,
1178 bool enable)
1172{ 1179{
1173 u32 val; 1180 u32 val;
1174 1181
@@ -1179,7 +1186,7 @@ static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1179 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1186 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1180} 1187}
1181 1188
1182static void dispc_ovl_enable_replication(enum omap_plane plane, 1189static void dispc_ovl_enable_replication(enum omap_plane_id plane,
1183 enum omap_overlay_caps caps, bool enable) 1190 enum omap_overlay_caps caps, bool enable)
1184{ 1191{
1185 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1192 static const unsigned shifts[] = { 5, 10, 10, 10 };
@@ -1276,7 +1283,7 @@ static void dispc_init_fifos(void)
1276 } 1283 }
1277} 1284}
1278 1285
1279static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) 1286static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane)
1280{ 1287{
1281 int fifo; 1288 int fifo;
1282 u32 size = 0; 1289 u32 size = 0;
@@ -1289,7 +1296,8 @@ static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1289 return size; 1296 return size;
1290} 1297}
1291 1298
1292void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) 1299void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
1300 u32 high)
1293{ 1301{
1294 u8 hi_start, hi_end, lo_start, lo_end; 1302 u8 hi_start, hi_end, lo_start, lo_end;
1295 u32 unit; 1303 u32 unit;
@@ -1338,7 +1346,7 @@ void dispc_enable_fifomerge(bool enable)
1338 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1346 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1339} 1347}
1340 1348
1341void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 1349void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
1342 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1350 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1343 bool manual_update) 1351 bool manual_update)
1344{ 1352{
@@ -1385,7 +1393,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1385 } 1393 }
1386} 1394}
1387 1395
1388static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable) 1396static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
1389{ 1397{
1390 int bit; 1398 int bit;
1391 1399
@@ -1397,7 +1405,7 @@ static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1397 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1405 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1398} 1406}
1399 1407
1400static void dispc_ovl_set_mflag_threshold(enum omap_plane plane, 1408static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane,
1401 int low, int high) 1409 int low, int high)
1402{ 1410{
1403 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1411 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
@@ -1461,7 +1469,7 @@ static void dispc_init_mflag(void)
1461 } 1469 }
1462} 1470}
1463 1471
1464static void dispc_ovl_set_fir(enum omap_plane plane, 1472static void dispc_ovl_set_fir(enum omap_plane_id plane,
1465 int hinc, int vinc, 1473 int hinc, int vinc,
1466 enum omap_color_component color_comp) 1474 enum omap_color_component color_comp)
1467{ 1475{
@@ -1484,7 +1492,8 @@ static void dispc_ovl_set_fir(enum omap_plane plane,
1484 } 1492 }
1485} 1493}
1486 1494
1487static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) 1495static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu,
1496 int vaccu)
1488{ 1497{
1489 u32 val; 1498 u32 val;
1490 u8 hor_start, hor_end, vert_start, vert_end; 1499 u8 hor_start, hor_end, vert_start, vert_end;
@@ -1498,7 +1507,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1498 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1507 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1499} 1508}
1500 1509
1501static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) 1510static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu,
1511 int vaccu)
1502{ 1512{
1503 u32 val; 1513 u32 val;
1504 u8 hor_start, hor_end, vert_start, vert_end; 1514 u8 hor_start, hor_end, vert_start, vert_end;
@@ -1512,7 +1522,7 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1512 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1522 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1513} 1523}
1514 1524
1515static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, 1525static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu,
1516 int vaccu) 1526 int vaccu)
1517{ 1527{
1518 u32 val; 1528 u32 val;
@@ -1521,7 +1531,7 @@ static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1521 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1531 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1522} 1532}
1523 1533
1524static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, 1534static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu,
1525 int vaccu) 1535 int vaccu)
1526{ 1536{
1527 u32 val; 1537 u32 val;
@@ -1530,7 +1540,7 @@ static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1530 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1540 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1531} 1541}
1532 1542
1533static void dispc_ovl_set_scale_param(enum omap_plane plane, 1543static void dispc_ovl_set_scale_param(enum omap_plane_id plane,
1534 u16 orig_width, u16 orig_height, 1544 u16 orig_width, u16 orig_height,
1535 u16 out_width, u16 out_height, 1545 u16 out_width, u16 out_height,
1536 bool five_taps, u8 rotation, 1546 bool five_taps, u8 rotation,
@@ -1546,7 +1556,7 @@ static void dispc_ovl_set_scale_param(enum omap_plane plane,
1546 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1556 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1547} 1557}
1548 1558
1549static void dispc_ovl_set_accu_uv(enum omap_plane plane, 1559static void dispc_ovl_set_accu_uv(enum omap_plane_id plane,
1550 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1560 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1551 bool ilace, enum omap_color_mode color_mode, u8 rotation) 1561 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1552{ 1562{
@@ -1634,7 +1644,7 @@ static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1634 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1644 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1635} 1645}
1636 1646
1637static void dispc_ovl_set_scaling_common(enum omap_plane plane, 1647static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
1638 u16 orig_width, u16 orig_height, 1648 u16 orig_width, u16 orig_height,
1639 u16 out_width, u16 out_height, 1649 u16 out_width, u16 out_height,
1640 bool ilace, bool five_taps, 1650 bool ilace, bool five_taps,
@@ -1688,7 +1698,7 @@ static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1688 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1698 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1689} 1699}
1690 1700
1691static void dispc_ovl_set_scaling_uv(enum omap_plane plane, 1701static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane,
1692 u16 orig_width, u16 orig_height, 1702 u16 orig_width, u16 orig_height,
1693 u16 out_width, u16 out_height, 1703 u16 out_width, u16 out_height,
1694 bool ilace, bool five_taps, 1704 bool ilace, bool five_taps,
@@ -1768,7 +1778,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1768 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1769} 1779}
1770 1780
1771static void dispc_ovl_set_scaling(enum omap_plane plane, 1781static void dispc_ovl_set_scaling(enum omap_plane_id plane,
1772 u16 orig_width, u16 orig_height, 1782 u16 orig_width, u16 orig_height,
1773 u16 out_width, u16 out_height, 1783 u16 out_width, u16 out_height,
1774 bool ilace, bool five_taps, 1784 bool ilace, bool five_taps,
@@ -1792,7 +1802,8 @@ static void dispc_ovl_set_scaling(enum omap_plane plane,
1792 rotation); 1802 rotation);
1793} 1803}
1794 1804
1795static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, 1805static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane,
1806 u8 rotation,
1796 enum omap_dss_rotation_type rotation_type, 1807 enum omap_dss_rotation_type rotation_type,
1797 bool mirroring, enum omap_color_mode color_mode) 1808 bool mirroring, enum omap_color_mode color_mode)
1798{ 1809{
@@ -2624,7 +2635,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2624 return 0; 2635 return 0;
2625} 2636}
2626 2637
2627static int dispc_ovl_setup_common(enum omap_plane plane, 2638static int dispc_ovl_setup_common(enum omap_plane_id plane,
2628 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2639 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2629 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2640 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2630 u16 out_width, u16 out_height, enum omap_color_mode color_mode, 2641 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
@@ -2822,7 +2833,8 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2822 return 0; 2833 return 0;
2823} 2834}
2824 2835
2825static int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 2836static int dispc_ovl_setup(enum omap_plane_id plane,
2837 const struct omap_overlay_info *oi,
2826 const struct videomode *vm, bool mem_to_mem) 2838 const struct videomode *vm, bool mem_to_mem)
2827{ 2839{
2828 int r; 2840 int r;
@@ -2852,7 +2864,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2852{ 2864{
2853 int r; 2865 int r;
2854 u32 l; 2866 u32 l;
2855 enum omap_plane plane = OMAP_DSS_WB; 2867 enum omap_plane_id plane = OMAP_DSS_WB;
2856 const int pos_x = 0, pos_y = 0; 2868 const int pos_x = 0, pos_y = 0;
2857 const u8 zorder = 0, global_alpha = 0; 2869 const u8 zorder = 0, global_alpha = 0;
2858 const bool replication = true; 2870 const bool replication = true;
@@ -2915,7 +2927,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2915 return r; 2927 return r;
2916} 2928}
2917 2929
2918static int dispc_ovl_enable(enum omap_plane plane, bool enable) 2930static int dispc_ovl_enable(enum omap_plane_id plane, bool enable)
2919{ 2931{
2920 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2932 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2921 2933
@@ -2924,7 +2936,7 @@ static int dispc_ovl_enable(enum omap_plane plane, bool enable)
2924 return 0; 2936 return 0;
2925} 2937}
2926 2938
2927static bool dispc_ovl_enabled(enum omap_plane plane) 2939static bool dispc_ovl_enabled(enum omap_plane_id plane)
2928{ 2940{
2929 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); 2941 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2930} 2942}
@@ -3392,7 +3404,7 @@ static unsigned long dispc_core_clk_rate(void)
3392 return dispc.core_clk_rate; 3404 return dispc.core_clk_rate;
3393} 3405}
3394 3406
3395static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) 3407static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane)
3396{ 3408{
3397 enum omap_channel channel; 3409 enum omap_channel channel;
3398 3410
@@ -3404,7 +3416,7 @@ static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3404 return dispc_mgr_pclk_rate(channel); 3416 return dispc_mgr_pclk_rate(channel);
3405} 3417}
3406 3418
3407static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) 3419static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane)
3408{ 3420{
3409 enum omap_channel channel; 3421 enum omap_channel channel;
3410 3422
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.h b/drivers/gpu/drm/omapdrm/dss/dispc.h
index bc1d8126ee87..003adce532f4 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.h
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.h
@@ -353,7 +353,7 @@ static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
353} 353}
354 354
355/* DISPC overlay register base addresses */ 355/* DISPC overlay register base addresses */
356static inline u16 DISPC_OVL_BASE(enum omap_plane plane) 356static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
357{ 357{
358 switch (plane) { 358 switch (plane) {
359 case OMAP_DSS_GFX: 359 case OMAP_DSS_GFX:
@@ -373,7 +373,7 @@ static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
373} 373}
374 374
375/* DISPC overlay register offsets */ 375/* DISPC overlay register offsets */
376static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane) 376static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
377{ 377{
378 switch (plane) { 378 switch (plane) {
379 case OMAP_DSS_GFX: 379 case OMAP_DSS_GFX:
@@ -389,7 +389,7 @@ static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
389 } 389 }
390} 390}
391 391
392static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane) 392static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
393{ 393{
394 switch (plane) { 394 switch (plane) {
395 case OMAP_DSS_GFX: 395 case OMAP_DSS_GFX:
@@ -405,7 +405,7 @@ static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
405 } 405 }
406} 406}
407 407
408static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane) 408static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
409{ 409{
410 switch (plane) { 410 switch (plane) {
411 case OMAP_DSS_GFX: 411 case OMAP_DSS_GFX:
@@ -425,7 +425,7 @@ static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
425 } 425 }
426} 426}
427 427
428static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane) 428static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
429{ 429{
430 switch (plane) { 430 switch (plane) {
431 case OMAP_DSS_GFX: 431 case OMAP_DSS_GFX:
@@ -445,7 +445,7 @@ static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
445 } 445 }
446} 446}
447 447
448static inline u16 DISPC_POS_OFFSET(enum omap_plane plane) 448static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
449{ 449{
450 switch (plane) { 450 switch (plane) {
451 case OMAP_DSS_GFX: 451 case OMAP_DSS_GFX:
@@ -460,7 +460,7 @@ static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
460 } 460 }
461} 461}
462 462
463static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane) 463static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
464{ 464{
465 switch (plane) { 465 switch (plane) {
466 case OMAP_DSS_GFX: 466 case OMAP_DSS_GFX:
@@ -476,7 +476,7 @@ static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
476 } 476 }
477} 477}
478 478
479static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane) 479static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
480{ 480{
481 switch (plane) { 481 switch (plane) {
482 case OMAP_DSS_GFX: 482 case OMAP_DSS_GFX:
@@ -493,7 +493,7 @@ static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
493 } 493 }
494} 494}
495 495
496static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane) 496static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
497{ 497{
498 switch (plane) { 498 switch (plane) {
499 case OMAP_DSS_GFX: 499 case OMAP_DSS_GFX:
@@ -513,7 +513,7 @@ static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
513 } 513 }
514} 514}
515 515
516static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane) 516static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
517{ 517{
518 switch (plane) { 518 switch (plane) {
519 case OMAP_DSS_GFX: 519 case OMAP_DSS_GFX:
@@ -530,7 +530,7 @@ static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
530 } 530 }
531} 531}
532 532
533static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane) 533static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
534{ 534{
535 switch (plane) { 535 switch (plane) {
536 case OMAP_DSS_GFX: 536 case OMAP_DSS_GFX:
@@ -547,7 +547,7 @@ static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
547 } 547 }
548} 548}
549 549
550static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane) 550static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
551{ 551{
552 switch (plane) { 552 switch (plane) {
553 case OMAP_DSS_GFX: 553 case OMAP_DSS_GFX:
@@ -564,7 +564,7 @@ static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
564 } 564 }
565} 565}
566 566
567static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane) 567static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
568{ 568{
569 switch (plane) { 569 switch (plane) {
570 case OMAP_DSS_GFX: 570 case OMAP_DSS_GFX:
@@ -581,7 +581,7 @@ static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
581 } 581 }
582} 582}
583 583
584static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane) 584static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
585{ 585{
586 switch (plane) { 586 switch (plane) {
587 case OMAP_DSS_GFX: 587 case OMAP_DSS_GFX:
@@ -597,7 +597,7 @@ static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
597 } 597 }
598} 598}
599 599
600static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane) 600static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
601{ 601{
602 switch (plane) { 602 switch (plane) {
603 case OMAP_DSS_GFX: 603 case OMAP_DSS_GFX:
@@ -613,7 +613,7 @@ static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
613 } 613 }
614} 614}
615 615
616static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane) 616static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
617{ 617{
618 switch (plane) { 618 switch (plane) {
619 case OMAP_DSS_GFX: 619 case OMAP_DSS_GFX:
@@ -631,7 +631,7 @@ static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
631 } 631 }
632} 632}
633 633
634static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane) 634static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
635{ 635{
636 switch (plane) { 636 switch (plane) {
637 case OMAP_DSS_GFX: 637 case OMAP_DSS_GFX:
@@ -651,7 +651,7 @@ static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
651 } 651 }
652} 652}
653 653
654static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane) 654static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
655{ 655{
656 switch (plane) { 656 switch (plane) {
657 case OMAP_DSS_GFX: 657 case OMAP_DSS_GFX:
@@ -670,7 +670,7 @@ static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
670} 670}
671 671
672 672
673static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane) 673static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
674{ 674{
675 switch (plane) { 675 switch (plane) {
676 case OMAP_DSS_GFX: 676 case OMAP_DSS_GFX:
@@ -688,7 +688,7 @@ static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
688 } 688 }
689} 689}
690 690
691static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane) 691static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
692{ 692{
693 switch (plane) { 693 switch (plane) {
694 case OMAP_DSS_GFX: 694 case OMAP_DSS_GFX:
@@ -708,7 +708,7 @@ static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
708 } 708 }
709} 709}
710 710
711static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane) 711static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
712{ 712{
713 switch (plane) { 713 switch (plane) {
714 case OMAP_DSS_GFX: 714 case OMAP_DSS_GFX:
@@ -726,7 +726,7 @@ static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
726 } 726 }
727} 727}
728 728
729static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane) 729static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
730{ 730{
731 switch (plane) { 731 switch (plane) {
732 case OMAP_DSS_GFX: 732 case OMAP_DSS_GFX:
@@ -747,7 +747,7 @@ static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
747} 747}
748 748
749/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 749/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
750static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i) 750static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
751{ 751{
752 switch (plane) { 752 switch (plane) {
753 case OMAP_DSS_GFX: 753 case OMAP_DSS_GFX:
@@ -766,7 +766,7 @@ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
766} 766}
767 767
768/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 768/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
769static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i) 769static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
770{ 770{
771 switch (plane) { 771 switch (plane) {
772 case OMAP_DSS_GFX: 772 case OMAP_DSS_GFX:
@@ -787,7 +787,7 @@ static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
787} 787}
788 788
789/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 789/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
790static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i) 790static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
791{ 791{
792 switch (plane) { 792 switch (plane) {
793 case OMAP_DSS_GFX: 793 case OMAP_DSS_GFX:
@@ -806,7 +806,7 @@ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
806} 806}
807 807
808/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 808/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
809static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i) 809static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
810{ 810{
811 switch (plane) { 811 switch (plane) {
812 case OMAP_DSS_GFX: 812 case OMAP_DSS_GFX:
@@ -827,7 +827,7 @@ static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
827} 827}
828 828
829/* coef index i = {0, 1, 2, 3, 4,} */ 829/* coef index i = {0, 1, 2, 3, 4,} */
830static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i) 830static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
831{ 831{
832 switch (plane) { 832 switch (plane) {
833 case OMAP_DSS_GFX: 833 case OMAP_DSS_GFX:
@@ -845,7 +845,7 @@ static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
845} 845}
846 846
847/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 847/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
848static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i) 848static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
849{ 849{
850 switch (plane) { 850 switch (plane) {
851 case OMAP_DSS_GFX: 851 case OMAP_DSS_GFX:
@@ -865,7 +865,7 @@ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
865} 865}
866 866
867/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ 867/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
868static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i) 868static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
869{ 869{
870 switch (plane) { 870 switch (plane) {
871 case OMAP_DSS_GFX: 871 case OMAP_DSS_GFX:
@@ -885,7 +885,7 @@ static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
885 } 885 }
886} 886}
887 887
888static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane) 888static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
889{ 889{
890 switch (plane) { 890 switch (plane) {
891 case OMAP_DSS_GFX: 891 case OMAP_DSS_GFX:
@@ -902,7 +902,7 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
902 } 902 }
903} 903}
904 904
905static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane) 905static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
906{ 906{
907 switch (plane) { 907 switch (plane) {
908 case OMAP_DSS_GFX: 908 case OMAP_DSS_GFX:
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index ab9f6afbf477..5dd29c98143a 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -359,8 +359,9 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
359 struct dispc_clock_info *cinfo); 359 struct dispc_clock_info *cinfo);
360 360
361 361
362void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high); 362void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
363void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 363 u32 high);
364void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
364 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 365 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
365 bool manual_update); 366 bool manual_update);
366 367
diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c
index 26c29332b8e3..80c6440a0e08 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss_features.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c
@@ -800,17 +800,17 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel
800 return omap_current_dss_features->supported_outputs[channel]; 800 return omap_current_dss_features->supported_outputs[channel];
801} 801}
802 802
803enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane) 803enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane)
804{ 804{
805 return omap_current_dss_features->supported_color_modes[plane]; 805 return omap_current_dss_features->supported_color_modes[plane];
806} 806}
807 807
808enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane) 808enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane)
809{ 809{
810 return omap_current_dss_features->overlay_caps[plane]; 810 return omap_current_dss_features->overlay_caps[plane];
811} 811}
812 812
813bool dss_feat_color_mode_supported(enum omap_plane plane, 813bool dss_feat_color_mode_supported(enum omap_plane_id plane,
814 enum omap_color_mode color_mode) 814 enum omap_color_mode color_mode)
815{ 815{
816 return omap_current_dss_features->supported_color_modes[plane] & 816 return omap_current_dss_features->supported_color_modes[plane] &
diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h
index bcec68ba8db9..27fbe64935e8 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss_features.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h
@@ -88,8 +88,8 @@ enum dss_range_param {
88/* DSS Feature Functions */ 88/* DSS Feature Functions */
89unsigned long dss_feat_get_param_min(enum dss_range_param param); 89unsigned long dss_feat_get_param_min(enum dss_range_param param);
90unsigned long dss_feat_get_param_max(enum dss_range_param param); 90unsigned long dss_feat_get_param_max(enum dss_range_param param);
91enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane); 91enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane);
92bool dss_feat_color_mode_supported(enum omap_plane plane, 92bool dss_feat_color_mode_supported(enum omap_plane_id plane,
93 enum omap_color_mode color_mode); 93 enum omap_color_mode color_mode);
94 94
95u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ 95u32 dss_feat_get_buffer_size_unit(void); /* in bytes */
@@ -106,6 +106,6 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel
106 106
107int dss_feat_get_num_mgrs(void); 107int dss_feat_get_num_mgrs(void);
108int dss_feat_get_num_ovls(void); 108int dss_feat_get_num_ovls(void);
109enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); 109enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane);
110 110
111#endif 111#endif
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index d5c369bd565c..63c2684f889b 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -76,7 +76,7 @@ enum omap_display_type {
76 OMAP_DISPLAY_TYPE_DVI = 1 << 6, 76 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
77}; 77};
78 78
79enum omap_plane { 79enum omap_plane_id {
80 OMAP_DSS_GFX = 0, 80 OMAP_DSS_GFX = 0,
81 OMAP_DSS_VIDEO1 = 1, 81 OMAP_DSS_VIDEO1 = 1,
82 OMAP_DSS_VIDEO2 = 2, 82 OMAP_DSS_VIDEO2 = 2,
@@ -338,7 +338,7 @@ struct omap_overlay {
338 338
339 /* static fields */ 339 /* static fields */
340 const char *name; 340 const char *name;
341 enum omap_plane id; 341 enum omap_plane_id id;
342 enum omap_color_mode supported_modes; 342 enum omap_color_mode supported_modes;
343 enum omap_overlay_caps caps; 343 enum omap_overlay_caps caps;
344 344
@@ -785,7 +785,7 @@ const char *omapdss_get_default_display_name(void);
785 785
786int dss_feat_get_num_mgrs(void); 786int dss_feat_get_num_mgrs(void);
787int dss_feat_get_num_ovls(void); 787int dss_feat_get_num_ovls(void);
788enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); 788enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane_id plane);
789 789
790 790
791 791
@@ -923,14 +923,15 @@ struct dispc_ops {
923 const struct drm_color_lut *lut, 923 const struct drm_color_lut *lut,
924 unsigned int length); 924 unsigned int length);
925 925
926 int (*ovl_enable)(enum omap_plane plane, bool enable); 926 int (*ovl_enable)(enum omap_plane_id plane, bool enable);
927 bool (*ovl_enabled)(enum omap_plane plane); 927 bool (*ovl_enabled)(enum omap_plane_id plane);
928 void (*ovl_set_channel_out)(enum omap_plane plane, 928 void (*ovl_set_channel_out)(enum omap_plane_id plane,
929 enum omap_channel channel); 929 enum omap_channel channel);
930 int (*ovl_setup)(enum omap_plane plane, const struct omap_overlay_info *oi, 930 int (*ovl_setup)(enum omap_plane_id plane,
931 const struct omap_overlay_info *oi,
931 const struct videomode *vm, bool mem_to_mem); 932 const struct videomode *vm, bool mem_to_mem);
932 933
933 enum omap_color_mode (*ovl_get_color_modes)(enum omap_plane plane); 934 enum omap_color_mode (*ovl_get_color_modes)(enum omap_plane_id plane);
934}; 935};
935 936
936void dispc_set_ops(const struct dispc_ops *o); 937void dispc_set_ops(const struct dispc_ops *o);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 00:55:19 -0500