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authorTomi Valkeinen <tomi.valkeinen@ti.com>2017-02-20 06:18:38 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2017-06-02 03:57:13 -0400
commit2e953d83a6797e4f1c6fe48c08fc9a8fcb50db78 (patch)
tree408ac35ef726950b7de27299c1dd325b572c0afd /drivers/gpu/drm/omapdrm
parent49a3057a5a2fa06264b0756cf417f75b56b7063b (diff)
drm/omap: remove read_irqenable()
We only use read_irqenable() to flush posted write. Instead of having a separate function for this, do the flush implicitly in write_irqenable(). Thus we can remove read_irqenable(). Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c9
-rw-r--r--drivers/gpu/drm/omapdrm/dss/omapdss.h1
-rw-r--r--drivers/gpu/drm/omapdrm/omap_irq.c1
3 files changed, 3 insertions, 8 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 05436eaad3ef..ac8ca605e314 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -3782,11 +3782,6 @@ static void dispc_clear_irqstatus(u32 mask)
3782 dispc_write_reg(DISPC_IRQSTATUS, mask); 3782 dispc_write_reg(DISPC_IRQSTATUS, mask);
3783} 3783}
3784 3784
3785static u32 dispc_read_irqenable(void)
3786{
3787 return dispc_read_reg(DISPC_IRQENABLE);
3788}
3789
3790static void dispc_write_irqenable(u32 mask) 3785static void dispc_write_irqenable(u32 mask)
3791{ 3786{
3792 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3787 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
@@ -3795,6 +3790,9 @@ static void dispc_write_irqenable(u32 mask)
3795 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3790 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3796 3791
3797 dispc_write_reg(DISPC_IRQENABLE, mask); 3792 dispc_write_reg(DISPC_IRQENABLE, mask);
3793
3794 /* flush posted write */
3795 dispc_read_reg(DISPC_IRQENABLE);
3798} 3796}
3799 3797
3800void dispc_enable_sidle(void) 3798void dispc_enable_sidle(void)
@@ -4345,7 +4343,6 @@ static void dispc_errata_i734_wa(void)
4345static const struct dispc_ops dispc_ops = { 4343static const struct dispc_ops dispc_ops = {
4346 .read_irqstatus = dispc_read_irqstatus, 4344 .read_irqstatus = dispc_read_irqstatus,
4347 .clear_irqstatus = dispc_clear_irqstatus, 4345 .clear_irqstatus = dispc_clear_irqstatus,
4348 .read_irqenable = dispc_read_irqenable,
4349 .write_irqenable = dispc_write_irqenable, 4346 .write_irqenable = dispc_write_irqenable,
4350 4347
4351 .request_irq = dispc_request_irq, 4348 .request_irq = dispc_request_irq,
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 72b0a508de67..8396036e210c 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -880,7 +880,6 @@ void dss_mgr_unregister_framedone_handler(enum omap_channel channel,
880struct dispc_ops { 880struct dispc_ops {
881 u32 (*read_irqstatus)(void); 881 u32 (*read_irqstatus)(void);
882 void (*clear_irqstatus)(u32 mask); 882 void (*clear_irqstatus)(u32 mask);
883 u32 (*read_irqenable)(void);
884 void (*write_irqenable)(u32 mask); 883 void (*write_irqenable)(u32 mask);
885 884
886 int (*request_irq)(irq_handler_t handler, void *dev_id); 885 int (*request_irq)(irq_handler_t handler, void *dev_id);
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c
index 115104cdcc59..7afe4b90befd 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.c
+++ b/drivers/gpu/drm/omapdrm/omap_irq.c
@@ -41,7 +41,6 @@ static void omap_irq_update(struct drm_device *dev)
41 DBG("irqmask=%08x", irqmask); 41 DBG("irqmask=%08x", irqmask);
42 42
43 priv->dispc_ops->write_irqenable(irqmask); 43 priv->dispc_ops->write_irqenable(irqmask);
44 priv->dispc_ops->read_irqenable(); /* flush posted write */
45} 44}
46 45
47static void omap_irq_wait_handler(struct omap_irq_wait *wait) 46static void omap_irq_wait_handler(struct omap_irq_wait *wait)