diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-05-17 09:08:34 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-05-19 13:19:06 -0400 |
commit | 01575776e54734eecab390df5aa1e047896ddacb (patch) | |
tree | 55830e58f1350925577df4054afa907f1fc79436 /drivers/gpu/drm/omapdrm | |
parent | 5670bd7219d774b2dc356edac36f9953f77e19a4 (diff) |
drm/omap: cleanup dispc_mgr_lclk_rate()
With the new PLL helpers, we can clean up the dispc_mgr_lclk_rate().
This will also make dispc_mgr_lclk_rate() support clock sources it
didn't support earlier.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dispc.c | 46 |
1 files changed, 17 insertions, 29 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 333a347f877b..01994d012ce4 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c | |||
@@ -3330,43 +3330,31 @@ static unsigned long dispc_fclk_rate(void) | |||
3330 | 3330 | ||
3331 | static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) | 3331 | static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
3332 | { | 3332 | { |
3333 | struct dss_pll *pll; | ||
3334 | int lcd; | 3333 | int lcd; |
3335 | unsigned long r; | 3334 | unsigned long r; |
3336 | u32 l; | 3335 | enum dss_clk_source src; |
3337 | |||
3338 | if (dss_mgr_is_lcd(channel)) { | ||
3339 | l = dispc_read_reg(DISPC_DIVISORo(channel)); | ||
3340 | 3336 | ||
3341 | lcd = FLD_GET(l, 23, 16); | 3337 | /* for TV, LCLK rate is the FCLK rate */ |
3338 | if (!dss_mgr_is_lcd(channel)) | ||
3339 | return dispc_fclk_rate(); | ||
3342 | 3340 | ||
3343 | switch (dss_get_lcd_clk_source(channel)) { | 3341 | src = dss_get_lcd_clk_source(channel); |
3344 | case DSS_CLK_SRC_FCK: | ||
3345 | r = dss_get_dispc_clk_rate(); | ||
3346 | break; | ||
3347 | case DSS_CLK_SRC_PLL1_1: | ||
3348 | pll = dss_pll_find("dsi0"); | ||
3349 | if (!pll) | ||
3350 | pll = dss_pll_find("video0"); | ||
3351 | 3342 | ||
3352 | r = pll->cinfo.clkout[0]; | 3343 | if (src == DSS_CLK_SRC_FCK) { |
3353 | break; | 3344 | r = dss_get_dispc_clk_rate(); |
3354 | case DSS_CLK_SRC_PLL2_1: | 3345 | } else { |
3355 | pll = dss_pll_find("dsi1"); | 3346 | struct dss_pll *pll; |
3356 | if (!pll) | 3347 | unsigned clkout_idx; |
3357 | pll = dss_pll_find("video1"); | ||
3358 | 3348 | ||
3359 | r = pll->cinfo.clkout[0]; | 3349 | pll = dss_pll_find_by_src(src); |
3360 | break; | 3350 | clkout_idx = dss_pll_get_clkout_idx_for_src(src); |
3361 | default: | ||
3362 | BUG(); | ||
3363 | return 0; | ||
3364 | } | ||
3365 | 3351 | ||
3366 | return r / lcd; | 3352 | r = pll->cinfo.clkout[clkout_idx]; |
3367 | } else { | ||
3368 | return dispc_fclk_rate(); | ||
3369 | } | 3353 | } |
3354 | |||
3355 | lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16); | ||
3356 | |||
3357 | return r / lcd; | ||
3370 | } | 3358 | } |
3371 | 3359 | ||
3372 | static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) | 3360 | static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |