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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2016-09-22 07:07:04 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2016-11-02 04:48:18 -0400
commitda11bbbb10a964c293c2e2e702ea62ad6cba48b4 (patch)
tree4ec07bad531ad4dbbe1e1cccef6f2a83ad9511a4 /drivers/gpu/drm/omapdrm/dss
parent4520ff28aaa1e7f1b45f3abc0c45429ea9e93817 (diff)
drm/omap: Use consistent name for struct videomode
Use 'vm' to refer to a struct videomode instead of 'p', 't', 'timings' or something else. The code will be easier to follow if we use consistent names. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss')
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c114
-rw-r--r--drivers/gpu/drm/omapdrm/dss/display.c8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dpi.c38
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dsi.c108
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.h5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi.h8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4.c32
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4_core.c8
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5.c32
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5_core.c68
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_wp.c58
-rw-r--r--drivers/gpu/drm/omapdrm/dss/omapdss.h57
-rw-r--r--drivers/gpu/drm/omapdrm/dss/output.c5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/rfbi.c52
-rw-r--r--drivers/gpu/drm/omapdrm/dss/sdi.c30
-rw-r--r--drivers/gpu/drm/omapdrm/dss/venc.c39
16 files changed, 328 insertions, 334 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index a5b7488a5cfb..c839f6456db2 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -75,7 +75,7 @@ struct dispc_features {
75 unsigned long max_lcd_pclk; 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk; 76 unsigned long max_tv_pclk;
77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
78 const struct videomode *mgr_timings, 78 const struct videomode *vm,
79 u16 width, u16 height, u16 out_width, u16 out_height, 79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps, 80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2179,7 +2179,7 @@ static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2179 * undocumented horizontal position and timing related limitations. 2179 * undocumented horizontal position and timing related limitations.
2180 */ 2180 */
2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, 2181static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2182 const struct videomode *t, u16 pos_x, 2182 const struct videomode *vm, u16 pos_x,
2183 u16 width, u16 height, u16 out_width, u16 out_height, 2183 u16 width, u16 height, u16 out_width, u16 out_height,
2184 bool five_taps) 2184 bool five_taps)
2185{ 2185{
@@ -2189,15 +2189,15 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2189 u64 val, blank; 2189 u64 val, blank;
2190 int i; 2190 int i;
2191 2191
2192 nonactive = t->hactive + t->hfront_porch + t->hsync_len + 2192 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len +
2193 t->hback_porch - out_width; 2193 vm->hback_porch - out_width;
2194 2194
2195 i = 0; 2195 i = 0;
2196 if (out_height < height) 2196 if (out_height < height)
2197 i++; 2197 i++;
2198 if (out_width < width) 2198 if (out_width < width)
2199 i++; 2199 i++;
2200 blank = div_u64((u64)(t->hback_porch + t->hsync_len + t->hfront_porch) * 2200 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) *
2201 lclk, pclk); 2201 lclk, pclk);
2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); 2202 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2203 if (blank <= limits[i]) 2203 if (blank <= limits[i])
@@ -2233,7 +2233,7 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2233} 2233}
2234 2234
2235static unsigned long calc_core_clk_five_taps(unsigned long pclk, 2235static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2236 const struct videomode *mgr_timings, u16 width, 2236 const struct videomode *vm, u16 width,
2237 u16 height, u16 out_width, u16 out_height, 2237 u16 height, u16 out_width, u16 out_height,
2238 enum omap_color_mode color_mode) 2238 enum omap_color_mode color_mode)
2239{ 2239{
@@ -2244,7 +2244,7 @@ static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2244 return (unsigned long) pclk; 2244 return (unsigned long) pclk;
2245 2245
2246 if (height > out_height) { 2246 if (height > out_height) {
2247 unsigned int ppl = mgr_timings->hactive; 2247 unsigned int ppl = vm->hactive;
2248 2248
2249 tmp = (u64)pclk * height * out_width; 2249 tmp = (u64)pclk * height * out_width;
2250 do_div(tmp, 2 * out_height * ppl); 2250 do_div(tmp, 2 * out_height * ppl);
@@ -2326,7 +2326,7 @@ static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2326} 2326}
2327 2327
2328static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2328static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2329 const struct videomode *mgr_timings, 2329 const struct videomode *vm,
2330 u16 width, u16 height, u16 out_width, u16 out_height, 2330 u16 width, u16 height, u16 out_width, u16 out_height,
2331 enum omap_color_mode color_mode, bool *five_taps, 2331 enum omap_color_mode color_mode, bool *five_taps,
2332 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2332 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2372,7 +2372,7 @@ static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2372} 2372}
2373 2373
2374static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2374static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2375 const struct videomode *mgr_timings, 2375 const struct videomode *vm,
2376 u16 width, u16 height, u16 out_width, u16 out_height, 2376 u16 width, u16 height, u16 out_width, u16 out_height,
2377 enum omap_color_mode color_mode, bool *five_taps, 2377 enum omap_color_mode color_mode, bool *five_taps,
2378 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2378 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2394,7 +2394,7 @@ static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2394 *five_taps = false; 2394 *five_taps = false;
2395again: 2395again:
2396 if (*five_taps) 2396 if (*five_taps)
2397 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, 2397 *core_clk = calc_core_clk_five_taps(pclk, vm,
2398 in_width, in_height, out_width, 2398 in_width, in_height, out_width,
2399 out_height, color_mode); 2399 out_height, color_mode);
2400 else 2400 else
@@ -2402,7 +2402,7 @@ again:
2402 in_height, out_width, out_height, 2402 in_height, out_width, out_height,
2403 mem_to_mem); 2403 mem_to_mem);
2404 2404
2405 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, 2405 error = check_horiz_timing_omap3(pclk, lclk, vm,
2406 pos_x, in_width, in_height, out_width, 2406 pos_x, in_width, in_height, out_width,
2407 out_height, *five_taps); 2407 out_height, *five_taps);
2408 if (error && *five_taps) { 2408 if (error && *five_taps) {
@@ -2437,7 +2437,7 @@ again:
2437 return -EINVAL; 2437 return -EINVAL;
2438 } 2438 }
2439 2439
2440 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width, 2440 if (check_horiz_timing_omap3(pclk, lclk, vm, pos_x, in_width,
2441 in_height, out_width, out_height, *five_taps)) { 2441 in_height, out_width, out_height, *five_taps)) {
2442 DSSERR("horizontal timing too tight\n"); 2442 DSSERR("horizontal timing too tight\n");
2443 return -EINVAL; 2443 return -EINVAL;
@@ -2457,7 +2457,7 @@ again:
2457} 2457}
2458 2458
2459static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2459static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2460 const struct videomode *mgr_timings, 2460 const struct videomode *vm,
2461 u16 width, u16 height, u16 out_width, u16 out_height, 2461 u16 width, u16 height, u16 out_width, u16 out_height,
2462 enum omap_color_mode color_mode, bool *five_taps, 2462 enum omap_color_mode color_mode, bool *five_taps,
2463 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2463 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
@@ -2503,7 +2503,7 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2503 2503
2504static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2504static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2505 enum omap_overlay_caps caps, 2505 enum omap_overlay_caps caps,
2506 const struct videomode *mgr_timings, 2506 const struct videomode *vm,
2507 u16 width, u16 height, u16 out_width, u16 out_height, 2507 u16 width, u16 height, u16 out_width, u16 out_height,
2508 enum omap_color_mode color_mode, bool *five_taps, 2508 enum omap_color_mode color_mode, bool *five_taps,
2509 int *x_predecim, int *y_predecim, u16 pos_x, 2509 int *x_predecim, int *y_predecim, u16 pos_x,
@@ -2517,7 +2517,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2517 if (width == out_width && height == out_height) 2517 if (width == out_width && height == out_height)
2518 return 0; 2518 return 0;
2519 2519
2520 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) { 2520 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2521 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2521 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2522 return -EINVAL; 2522 return -EINVAL;
2523 } 2523 }
@@ -2553,7 +2553,7 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2553 if (decim_y > *y_predecim || out_height > height * 8) 2553 if (decim_y > *y_predecim || out_height > height * 8)
2554 return -EINVAL; 2554 return -EINVAL;
2555 2555
2556 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, 2556 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height,
2557 out_width, out_height, color_mode, five_taps, 2557 out_width, out_height, color_mode, five_taps,
2558 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2558 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2559 mem_to_mem); 2559 mem_to_mem);
@@ -2593,7 +2593,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2593 u16 out_width, u16 out_height, enum omap_color_mode color_mode, 2593 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2594 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, 2594 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2595 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2595 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2596 bool replication, const struct videomode *mgr_timings, 2596 bool replication, const struct videomode *vm,
2597 bool mem_to_mem) 2597 bool mem_to_mem)
2598{ 2598{
2599 bool five_taps = true; 2599 bool five_taps = true;
@@ -2607,7 +2607,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2607 u16 in_height = height; 2607 u16 in_height = height;
2608 u16 in_width = width; 2608 u16 in_width = width;
2609 int x_predecim = 1, y_predecim = 1; 2609 int x_predecim = 1, y_predecim = 1;
2610 bool ilace = !!(mgr_timings->flags & DISPLAY_FLAGS_INTERLACED); 2610 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2611 unsigned long pclk = dispc_plane_pclk_rate(plane); 2611 unsigned long pclk = dispc_plane_pclk_rate(plane);
2612 unsigned long lclk = dispc_plane_lclk_rate(plane); 2612 unsigned long lclk = dispc_plane_lclk_rate(plane);
2613 2613
@@ -2649,7 +2649,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2649 if (!dss_feat_color_mode_supported(plane, color_mode)) 2649 if (!dss_feat_color_mode_supported(plane, color_mode))
2650 return -EINVAL; 2650 return -EINVAL;
2651 2651
2652 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, 2652 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width,
2653 in_height, out_width, out_height, color_mode, 2653 in_height, out_width, out_height, color_mode,
2654 &five_taps, &x_predecim, &y_predecim, pos_x, 2654 &five_taps, &x_predecim, &y_predecim, pos_x,
2655 rotation_type, mem_to_mem); 2655 rotation_type, mem_to_mem);
@@ -2786,7 +2786,7 @@ static int dispc_ovl_setup_common(enum omap_plane plane,
2786} 2786}
2787 2787
2788int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 2788int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2789 bool replication, const struct videomode *mgr_timings, 2789 bool replication, const struct videomode *vm,
2790 bool mem_to_mem) 2790 bool mem_to_mem)
2791{ 2791{
2792 int r; 2792 int r;
@@ -2805,14 +2805,14 @@ int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2805 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2805 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2806 oi->out_width, oi->out_height, oi->color_mode, oi->rotation, 2806 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2807 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2807 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2808 oi->rotation_type, replication, mgr_timings, mem_to_mem); 2808 oi->rotation_type, replication, vm, mem_to_mem);
2809 2809
2810 return r; 2810 return r;
2811} 2811}
2812EXPORT_SYMBOL(dispc_ovl_setup); 2812EXPORT_SYMBOL(dispc_ovl_setup);
2813 2813
2814int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2814int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2815 bool mem_to_mem, const struct videomode *mgr_timings) 2815 bool mem_to_mem, const struct videomode *vm)
2816{ 2816{
2817 int r; 2817 int r;
2818 u32 l; 2818 u32 l;
@@ -2821,8 +2821,8 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2821 const u8 zorder = 0, global_alpha = 0; 2821 const u8 zorder = 0, global_alpha = 0;
2822 const bool replication = false; 2822 const bool replication = false;
2823 bool truncation; 2823 bool truncation;
2824 int in_width = mgr_timings->hactive; 2824 int in_width = vm->hactive;
2825 int in_height = mgr_timings->vactive; 2825 int in_height = vm->vactive;
2826 enum omap_overlay_caps caps = 2826 enum omap_overlay_caps caps =
2827 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2827 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2828 2828
@@ -2835,7 +2835,7 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2835 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2835 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2836 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, 2836 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2837 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2837 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2838 replication, mgr_timings, mem_to_mem); 2838 replication, vm, mem_to_mem);
2839 2839
2840 switch (wi->color_mode) { 2840 switch (wi->color_mode) {
2841 case OMAP_DSS_COLOR_RGB16: 2841 case OMAP_DSS_COLOR_RGB16:
@@ -2869,9 +2869,8 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2869 } else { 2869 } else {
2870 int wbdelay; 2870 int wbdelay;
2871 2871
2872 wbdelay = min(mgr_timings->vfront_porch + 2872 wbdelay = min(vm->vfront_porch +
2873 mgr_timings->vsync_len + mgr_timings->vback_porch, 2873 vm->vsync_len + vm->vback_porch, (u32)255);
2874 (u32)255);
2875 2874
2876 /* WBDELAYCOUNT */ 2875 /* WBDELAYCOUNT */
2877 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2876 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
@@ -3118,24 +3117,23 @@ static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3118 return pclk <= dispc.feat->max_tv_pclk; 3117 return pclk <= dispc.feat->max_tv_pclk;
3119} 3118}
3120 3119
3121bool dispc_mgr_timings_ok(enum omap_channel channel, 3120bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
3122 const struct videomode *timings)
3123{ 3121{
3124 if (!_dispc_mgr_size_ok(timings->hactive, timings->vactive)) 3122 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive))
3125 return false; 3123 return false;
3126 3124
3127 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) 3125 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock))
3128 return false; 3126 return false;
3129 3127
3130 if (dss_mgr_is_lcd(channel)) { 3128 if (dss_mgr_is_lcd(channel)) {
3131 /* TODO: OMAP4+ supports interlace for LCD outputs */ 3129 /* TODO: OMAP4+ supports interlace for LCD outputs */
3132 if (timings->flags & DISPLAY_FLAGS_INTERLACED) 3130 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
3133 return false; 3131 return false;
3134 3132
3135 if (!_dispc_lcd_timings_ok(timings->hsync_len, 3133 if (!_dispc_lcd_timings_ok(vm->hsync_len,
3136 timings->hfront_porch, timings->hback_porch, 3134 vm->hfront_porch, vm->hback_porch,
3137 timings->vsync_len, timings->vfront_porch, 3135 vm->vsync_len, vm->vfront_porch,
3138 timings->vback_porch)) 3136 vm->vback_porch))
3139 return false; 3137 return false;
3140 } 3138 }
3141 3139
@@ -3143,37 +3141,37 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
3143} 3141}
3144 3142
3145static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, 3143static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3146 const struct videomode *ovt) 3144 const struct videomode *vm)
3147{ 3145{
3148 u32 timing_h, timing_v, l; 3146 u32 timing_h, timing_v, l;
3149 bool onoff, rf, ipc, vs, hs, de; 3147 bool onoff, rf, ipc, vs, hs, de;
3150 3148
3151 timing_h = FLD_VAL(ovt->hsync_len - 1, dispc.feat->sw_start, 0) | 3149 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) |
3152 FLD_VAL(ovt->hfront_porch - 1, dispc.feat->fp_start, 8) | 3150 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) |
3153 FLD_VAL(ovt->hback_porch - 1, dispc.feat->bp_start, 20); 3151 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20);
3154 timing_v = FLD_VAL(ovt->vsync_len - 1, dispc.feat->sw_start, 0) | 3152 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) |
3155 FLD_VAL(ovt->vfront_porch, dispc.feat->fp_start, 8) | 3153 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) |
3156 FLD_VAL(ovt->vback_porch, dispc.feat->bp_start, 20); 3154 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20);
3157 3155
3158 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 3156 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3159 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 3157 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3160 3158
3161 if (ovt->flags & DISPLAY_FLAGS_VSYNC_HIGH) 3159 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
3162 vs = false; 3160 vs = false;
3163 else 3161 else
3164 vs = true; 3162 vs = true;
3165 3163
3166 if (ovt->flags & DISPLAY_FLAGS_HSYNC_HIGH) 3164 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
3167 hs = false; 3165 hs = false;
3168 else 3166 else
3169 hs = true; 3167 hs = true;
3170 3168
3171 if (ovt->flags & DISPLAY_FLAGS_DE_HIGH) 3169 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
3172 de = false; 3170 de = false;
3173 else 3171 else
3174 de = true; 3172 de = true;
3175 3173
3176 if (ovt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) 3174 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
3177 ipc = false; 3175 ipc = false;
3178 else 3176 else
3179 ipc = true; 3177 ipc = true;
@@ -3181,7 +3179,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3181 /* always use the 'rf' setting */ 3179 /* always use the 'rf' setting */
3182 onoff = true; 3180 onoff = true;
3183 3181
3184 if (ovt->flags & DISPLAY_FLAGS_SYNC_POSEDGE) 3182 if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE)
3185 rf = true; 3183 rf = true;
3186 else 3184 else
3187 rf = false; 3185 rf = false;
@@ -3221,11 +3219,11 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3221 3219
3222/* change name to mode? */ 3220/* change name to mode? */
3223void dispc_mgr_set_timings(enum omap_channel channel, 3221void dispc_mgr_set_timings(enum omap_channel channel,
3224 const struct videomode *timings) 3222 const struct videomode *vm)
3225{ 3223{
3226 unsigned xtot, ytot; 3224 unsigned xtot, ytot;
3227 unsigned long ht, vt; 3225 unsigned long ht, vt;
3228 struct videomode t = *timings; 3226 struct videomode t = *vm;
3229 3227
3230 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 3228 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3231 3229
@@ -3240,10 +3238,10 @@ void dispc_mgr_set_timings(enum omap_channel channel,
3240 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3238 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3241 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 3239 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
3242 3240
3243 ht = timings->pixelclock / xtot; 3241 ht = vm->pixelclock / xtot;
3244 vt = timings->pixelclock / xtot / ytot; 3242 vt = vm->pixelclock / xtot / ytot;
3245 3243
3246 DSSDBG("pck %lu\n", timings->pixelclock); 3244 DSSDBG("pck %lu\n", vm->pixelclock);
3247 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", 3245 DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3248 t.hsync_len, t.hfront_porch, t.hback_porch, 3246 t.hsync_len, t.hfront_porch, t.hback_porch,
3249 t.vsync_len, t.vfront_porch, t.vback_porch); 3247 t.vsync_len, t.vfront_porch, t.vback_porch);
@@ -4185,12 +4183,12 @@ EXPORT_SYMBOL(dispc_free_irq);
4185 */ 4183 */
4186 4184
4187static const struct dispc_errata_i734_data { 4185static const struct dispc_errata_i734_data {
4188 struct videomode timings; 4186 struct videomode vm;
4189 struct omap_overlay_info ovli; 4187 struct omap_overlay_info ovli;
4190 struct omap_overlay_manager_info mgri; 4188 struct omap_overlay_manager_info mgri;
4191 struct dss_lcd_mgr_config lcd_conf; 4189 struct dss_lcd_mgr_config lcd_conf;
4192} i734 = { 4190} i734 = {
4193 .timings = { 4191 .vm = {
4194 .hactive = 8, .vactive = 1, 4192 .hactive = 8, .vactive = 1,
4195 .pixelclock = 16000000, 4193 .pixelclock = 16000000,
4196 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, 4194 .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
@@ -4288,7 +4286,7 @@ static void dispc_errata_i734_wa(void)
4288 4286
4289 /* Setup and enable GFX plane */ 4287 /* Setup and enable GFX plane */
4290 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD); 4288 dispc_ovl_set_channel_out(OMAP_DSS_GFX, OMAP_DSS_CHANNEL_LCD);
4291 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.timings, false); 4289 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, false, &i734.vm, false);
4292 dispc_ovl_enable(OMAP_DSS_GFX, true); 4290 dispc_ovl_enable(OMAP_DSS_GFX, true);
4293 4291
4294 /* Set up and enable display manager for LCD1 */ 4292 /* Set up and enable display manager for LCD1 */
@@ -4296,7 +4294,7 @@ static void dispc_errata_i734_wa(void)
4296 dispc_calc_clock_rates(dss_get_dispc_clk_rate(), 4294 dispc_calc_clock_rates(dss_get_dispc_clk_rate(),
4297 &lcd_conf.clock_info); 4295 &lcd_conf.clock_info);
4298 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4296 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4299 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.timings); 4297 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm);
4300 4298
4301 dispc_clear_irqstatus(framedone_irq); 4299 dispc_clear_irqstatus(framedone_irq);
4302 4300
diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c
index 56cc071b6223..425a5a8dff8b 100644
--- a/drivers/gpu/drm/omapdrm/dss/display.c
+++ b/drivers/gpu/drm/omapdrm/dss/display.c
@@ -35,8 +35,8 @@
35void omapdss_default_get_resolution(struct omap_dss_device *dssdev, 35void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
36 u16 *xres, u16 *yres) 36 u16 *xres, u16 *yres)
37{ 37{
38 *xres = dssdev->panel.timings.hactive; 38 *xres = dssdev->panel.vm.hactive;
39 *yres = dssdev->panel.timings.vactive; 39 *yres = dssdev->panel.vm.vactive;
40} 40}
41EXPORT_SYMBOL(omapdss_default_get_resolution); 41EXPORT_SYMBOL(omapdss_default_get_resolution);
42 42
@@ -72,9 +72,9 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
72EXPORT_SYMBOL(omapdss_default_get_recommended_bpp); 72EXPORT_SYMBOL(omapdss_default_get_recommended_bpp);
73 73
74void omapdss_default_get_timings(struct omap_dss_device *dssdev, 74void omapdss_default_get_timings(struct omap_dss_device *dssdev,
75 struct videomode *timings) 75 struct videomode *vm)
76{ 76{
77 *timings = dssdev->panel.timings; 77 *vm = dssdev->panel.vm;
78} 78}
79EXPORT_SYMBOL(omapdss_default_get_timings); 79EXPORT_SYMBOL(omapdss_default_get_timings);
80 80
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index 178335094288..e75162d26ac0 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -47,7 +47,7 @@ struct dpi_data {
47 47
48 struct mutex lock; 48 struct mutex lock;
49 49
50 struct videomode timings; 50 struct videomode vm;
51 struct dss_lcd_mgr_config mgr_config; 51 struct dss_lcd_mgr_config mgr_config;
52 int data_lines; 52 int data_lines;
53 53
@@ -333,31 +333,31 @@ static int dpi_set_mode(struct dpi_data *dpi)
333{ 333{
334 struct omap_dss_device *out = &dpi->output; 334 struct omap_dss_device *out = &dpi->output;
335 enum omap_channel channel = out->dispc_channel; 335 enum omap_channel channel = out->dispc_channel;
336 struct videomode *t = &dpi->timings; 336 struct videomode *vm = &dpi->vm;
337 int lck_div = 0, pck_div = 0; 337 int lck_div = 0, pck_div = 0;
338 unsigned long fck = 0; 338 unsigned long fck = 0;
339 unsigned long pck; 339 unsigned long pck;
340 int r = 0; 340 int r = 0;
341 341
342 if (dpi->pll) 342 if (dpi->pll)
343 r = dpi_set_pll_clk(dpi, channel, t->pixelclock, &fck, 343 r = dpi_set_pll_clk(dpi, channel, vm->pixelclock, &fck,
344 &lck_div, &pck_div); 344 &lck_div, &pck_div);
345 else 345 else
346 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck, 346 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck,
347 &lck_div, &pck_div); 347 &lck_div, &pck_div);
348 if (r) 348 if (r)
349 return r; 349 return r;
350 350
351 pck = fck / lck_div / pck_div; 351 pck = fck / lck_div / pck_div;
352 352
353 if (pck != t->pixelclock) { 353 if (pck != vm->pixelclock) {
354 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 354 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
355 t->pixelclock, pck); 355 vm->pixelclock, pck);
356 356
357 t->pixelclock = pck; 357 vm->pixelclock = pck;
358 } 358 }
359 359
360 dss_mgr_set_timings(channel, t); 360 dss_mgr_set_timings(channel, vm);
361 361
362 return 0; 362 return 0;
363} 363}
@@ -476,7 +476,7 @@ static void dpi_display_disable(struct omap_dss_device *dssdev)
476} 476}
477 477
478static void dpi_set_timings(struct omap_dss_device *dssdev, 478static void dpi_set_timings(struct omap_dss_device *dssdev,
479 struct videomode *timings) 479 struct videomode *vm)
480{ 480{
481 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 481 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
482 482
@@ -484,25 +484,25 @@ static void dpi_set_timings(struct omap_dss_device *dssdev,
484 484
485 mutex_lock(&dpi->lock); 485 mutex_lock(&dpi->lock);
486 486
487 dpi->timings = *timings; 487 dpi->vm = *vm;
488 488
489 mutex_unlock(&dpi->lock); 489 mutex_unlock(&dpi->lock);
490} 490}
491 491
492static void dpi_get_timings(struct omap_dss_device *dssdev, 492static void dpi_get_timings(struct omap_dss_device *dssdev,
493 struct videomode *timings) 493 struct videomode *vm)
494{ 494{
495 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 495 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
496 496
497 mutex_lock(&dpi->lock); 497 mutex_lock(&dpi->lock);
498 498
499 *timings = dpi->timings; 499 *vm = dpi->vm;
500 500
501 mutex_unlock(&dpi->lock); 501 mutex_unlock(&dpi->lock);
502} 502}
503 503
504static int dpi_check_timings(struct omap_dss_device *dssdev, 504static int dpi_check_timings(struct omap_dss_device *dssdev,
505 struct videomode *timings) 505 struct videomode *vm)
506{ 506{
507 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 507 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
508 enum omap_channel channel = dpi->output.dispc_channel; 508 enum omap_channel channel = dpi->output.dispc_channel;
@@ -512,23 +512,23 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
512 struct dpi_clk_calc_ctx ctx; 512 struct dpi_clk_calc_ctx ctx;
513 bool ok; 513 bool ok;
514 514
515 if (timings->hactive % 8 != 0) 515 if (vm->hactive % 8 != 0)
516 return -EINVAL; 516 return -EINVAL;
517 517
518 if (!dispc_mgr_timings_ok(channel, timings)) 518 if (!dispc_mgr_timings_ok(channel, vm))
519 return -EINVAL; 519 return -EINVAL;
520 520
521 if (timings->pixelclock == 0) 521 if (vm->pixelclock == 0)
522 return -EINVAL; 522 return -EINVAL;
523 523
524 if (dpi->pll) { 524 if (dpi->pll) {
525 ok = dpi_pll_clk_calc(dpi, timings->pixelclock, &ctx); 525 ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx);
526 if (!ok) 526 if (!ok)
527 return -EINVAL; 527 return -EINVAL;
528 528
529 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 529 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
530 } else { 530 } else {
531 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); 531 ok = dpi_dss_clk_calc(vm->pixelclock, &ctx);
532 if (!ok) 532 if (!ok)
533 return -EINVAL; 533 return -EINVAL;
534 534
@@ -540,7 +540,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
540 540
541 pck = fck / lck_div / pck_div; 541 pck = fck / lck_div / pck_div;
542 542
543 timings->pixelclock = pck; 543 vm->pixelclock = pck;
544 544
545 return 0; 545 return 0;
546} 546}
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 13569cb3f786..f060bda31235 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -289,7 +289,7 @@ struct dsi_clk_calc_ctx {
289 struct dss_pll_clock_info dsi_cinfo; 289 struct dss_pll_clock_info dsi_cinfo;
290 struct dispc_clock_info dispc_cinfo; 290 struct dispc_clock_info dispc_cinfo;
291 291
292 struct videomode dispc_vm; 292 struct videomode vm;
293 struct omap_dss_dsi_videomode_timings dsi_vm; 293 struct omap_dss_dsi_videomode_timings dsi_vm;
294}; 294};
295 295
@@ -383,7 +383,7 @@ struct dsi_data {
383 unsigned scp_clk_refcount; 383 unsigned scp_clk_refcount;
384 384
385 struct dss_lcd_mgr_config mgr_config; 385 struct dss_lcd_mgr_config mgr_config;
386 struct videomode timings; 386 struct videomode vm;
387 enum omap_dss_dsi_pixel_format pix_fmt; 387 enum omap_dss_dsi_pixel_format pix_fmt;
388 enum omap_dss_dsi_mode mode; 388 enum omap_dss_dsi_mode mode;
389 struct omap_dss_dsi_videomode_timings vm_timings; 389 struct omap_dss_dsi_videomode_timings vm_timings;
@@ -3321,12 +3321,12 @@ static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3321 3321
3322 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3322 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3323 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3323 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3324 struct videomode *timings = &dsi->timings; 3324 struct videomode *vm = &dsi->vm;
3325 /* 3325 /*
3326 * Don't use line buffers if width is greater than the video 3326 * Don't use line buffers if width is greater than the video
3327 * port's line buffer size 3327 * port's line buffer size
3328 */ 3328 */
3329 if (dsi->line_buffer_size <= timings->hactive * bpp / 8) 3329 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3330 num_line_buffers = 0; 3330 num_line_buffers = 0;
3331 else 3331 else
3332 num_line_buffers = 2; 3332 num_line_buffers = 2;
@@ -3453,7 +3453,7 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3453 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3453 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3454 int tclk_trail, ths_exit, exiths_clk; 3454 int tclk_trail, ths_exit, exiths_clk;
3455 bool ddr_alwon; 3455 bool ddr_alwon;
3456 struct videomode *timings = &dsi->timings; 3456 struct videomode *vm = &dsi->vm;
3457 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3457 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3458 int ndl = dsi->num_lanes_used - 1; 3458 int ndl = dsi->num_lanes_used - 1;
3459 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3459 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
@@ -3494,7 +3494,7 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3494 3494
3495 exiths_clk = ths_exit + tclk_trail; 3495 exiths_clk = ths_exit + tclk_trail;
3496 3496
3497 width_bytes = DIV_ROUND_UP(timings->hactive * bpp, 8); 3497 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3498 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3498 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3499 3499
3500 if (!hsa_blanking_mode) { 3500 if (!hsa_blanking_mode) {
@@ -3705,7 +3705,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3705 int vbp = dsi->vm_timings.vbp; 3705 int vbp = dsi->vm_timings.vbp;
3706 int window_sync = dsi->vm_timings.window_sync; 3706 int window_sync = dsi->vm_timings.window_sync;
3707 bool hsync_end; 3707 bool hsync_end;
3708 struct videomode *timings = &dsi->timings; 3708 struct videomode *vm = &dsi->vm;
3709 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3709 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3710 int tl, t_he, width_bytes; 3710 int tl, t_he, width_bytes;
3711 3711
@@ -3713,7 +3713,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3713 t_he = hsync_end ? 3713 t_he = hsync_end ?
3714 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3714 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3715 3715
3716 width_bytes = DIV_ROUND_UP(timings->hactive * bpp, 8); 3716 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3717 3717
3718 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3718 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3719 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3719 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
@@ -3722,7 +3722,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3722 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3722 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3723 hfp, hsync_end ? hsa : 0, tl); 3723 hfp, hsync_end ? hsa : 0, tl);
3724 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3724 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3725 vsa, timings->vactive); 3725 vsa, vm->vactive);
3726 3726
3727 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3727 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3728 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3728 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
@@ -3738,7 +3738,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3738 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3738 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3739 3739
3740 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3740 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3741 r = FLD_MOD(r, timings->vactive, 14, 0); /* VACT */ 3741 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3742 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3742 r = FLD_MOD(r, tl, 31, 16); /* TL */
3743 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3743 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3744 } 3744 }
@@ -3856,7 +3856,7 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3856 /* MODE, 1 = video mode */ 3856 /* MODE, 1 = video mode */
3857 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3857 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3858 3858
3859 word_count = DIV_ROUND_UP(dsi->timings.hactive * bpp, 8); 3859 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3860 3860
3861 dsi_vc_write_long_header(dsidev, channel, data_type, 3861 dsi_vc_write_long_header(dsidev, channel, data_type,
3862 word_count, 0); 3862 word_count, 0);
@@ -3918,8 +3918,8 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
3918 int r; 3918 int r;
3919 const unsigned channel = dsi->update_channel; 3919 const unsigned channel = dsi->update_channel;
3920 const unsigned line_buf_size = dsi->line_buffer_size; 3920 const unsigned line_buf_size = dsi->line_buffer_size;
3921 u16 w = dsi->timings.hactive; 3921 u16 w = dsi->vm.hactive;
3922 u16 h = dsi->timings.vactive; 3922 u16 h = dsi->vm.vactive;
3923 3923
3924 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3924 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3925 3925
@@ -3969,7 +3969,7 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
3969 msecs_to_jiffies(250)); 3969 msecs_to_jiffies(250));
3970 BUG_ON(r == 0); 3970 BUG_ON(r == 0);
3971 3971
3972 dss_mgr_set_timings(dispc_channel, &dsi->timings); 3972 dss_mgr_set_timings(dispc_channel, &dsi->vm);
3973 3973
3974 dss_mgr_start_update(dispc_channel); 3974 dss_mgr_start_update(dispc_channel);
3975 3975
@@ -4056,8 +4056,8 @@ static int dsi_update(struct omap_dss_device *dssdev, int channel,
4056 dsi->framedone_callback = callback; 4056 dsi->framedone_callback = callback;
4057 dsi->framedone_data = data; 4057 dsi->framedone_data = data;
4058 4058
4059 dw = dsi->timings.hactive; 4059 dw = dsi->vm.hactive;
4060 dh = dsi->timings.vactive; 4060 dh = dsi->vm.vactive;
4061 4061
4062#ifdef DSI_PERF_MEASURE 4062#ifdef DSI_PERF_MEASURE
4063 dsi->update_bytes = dw * dh * 4063 dsi->update_bytes = dw * dh *
@@ -4122,19 +4122,19 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
4122 * override interlace, logic level and edge related parameters in 4122 * override interlace, logic level and edge related parameters in
4123 * videomode with default values 4123 * videomode with default values
4124 */ 4124 */
4125 dsi->timings.flags &= ~DISPLAY_FLAGS_INTERLACED; 4125 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4126 dsi->timings.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4126 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4127 dsi->timings.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4127 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4128 dsi->timings.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4128 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4129 dsi->timings.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4129 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4130 dsi->timings.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4130 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4131 dsi->timings.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4131 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4132 dsi->timings.flags &= ~DISPLAY_FLAGS_DE_LOW; 4132 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4133 dsi->timings.flags |= DISPLAY_FLAGS_DE_HIGH; 4133 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4134 dsi->timings.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4134 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4135 dsi->timings.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4135 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4136 4136
4137 dss_mgr_set_timings(channel, &dsi->timings); 4137 dss_mgr_set_timings(channel, &dsi->vm);
4138 4138
4139 r = dsi_configure_dispc_clocks(dsidev); 4139 r = dsi_configure_dispc_clocks(dsidev);
4140 if (r) 4140 if (r)
@@ -4361,13 +4361,13 @@ static void print_dsi_vm(const char *str,
4361#undef TO_DSI_T 4361#undef TO_DSI_T
4362} 4362}
4363 4363
4364static void print_dispc_vm(const char *str, const struct videomode *t) 4364static void print_dispc_vm(const char *str, const struct videomode *vm)
4365{ 4365{
4366 unsigned long pck = t->pixelclock; 4366 unsigned long pck = vm->pixelclock;
4367 int hact, bl, tot; 4367 int hact, bl, tot;
4368 4368
4369 hact = t->hactive; 4369 hact = vm->hactive;
4370 bl = t->hsync_len + t->hbp + t->hfront_porch; 4370 bl = vm->hsync_len + vm->hbp + vm->hfront_porch;
4371 tot = hact + bl; 4371 tot = hact + bl;
4372 4372
4373#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4373#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
@@ -4376,12 +4376,12 @@ static void print_dispc_vm(const char *str, const struct videomode *t)
4376 "%u/%u/%u/%u = %u + %u = %u\n", 4376 "%u/%u/%u/%u = %u + %u = %u\n",
4377 str, 4377 str,
4378 pck, 4378 pck,
4379 t->hsync_len, t->hbp, hact, t->hfront_porch, 4379 vm->hsync_len, vm->hbp, hact, vm->hfront_porch,
4380 bl, hact, tot, 4380 bl, hact, tot,
4381 TO_DISPC_T(t->hsync_len), 4381 TO_DISPC_T(vm->hsync_len),
4382 TO_DISPC_T(t->hbp), 4382 TO_DISPC_T(vm->hbp),
4383 TO_DISPC_T(hact), 4383 TO_DISPC_T(hact),
4384 TO_DISPC_T(t->hfront_porch), 4384 TO_DISPC_T(vm->hfront_porch),
4385 TO_DISPC_T(bl), 4385 TO_DISPC_T(bl),
4386 TO_DISPC_T(hact), 4386 TO_DISPC_T(hact),
4387 TO_DISPC_T(tot)); 4387 TO_DISPC_T(tot));
@@ -4417,19 +4417,19 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4417 unsigned long pck, void *data) 4417 unsigned long pck, void *data)
4418{ 4418{
4419 struct dsi_clk_calc_ctx *ctx = data; 4419 struct dsi_clk_calc_ctx *ctx = data;
4420 struct videomode *t = &ctx->dispc_vm; 4420 struct videomode *vm = &ctx->vm;
4421 4421
4422 ctx->dispc_cinfo.lck_div = lckd; 4422 ctx->dispc_cinfo.lck_div = lckd;
4423 ctx->dispc_cinfo.pck_div = pckd; 4423 ctx->dispc_cinfo.pck_div = pckd;
4424 ctx->dispc_cinfo.lck = lck; 4424 ctx->dispc_cinfo.lck = lck;
4425 ctx->dispc_cinfo.pck = pck; 4425 ctx->dispc_cinfo.pck = pck;
4426 4426
4427 *t = *ctx->config->timings; 4427 *vm = *ctx->config->vm;
4428 t->pixelclock = pck; 4428 vm->pixelclock = pck;
4429 t->hactive = ctx->config->timings->hactive; 4429 vm->hactive = ctx->config->vm->hactive;
4430 t->vactive = ctx->config->timings->vactive; 4430 vm->vactive = ctx->config->vm->vactive;
4431 t->hsync_len = t->hfront_porch = t->hback_porch = t->vsync_len = 1; 4431 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4432 t->vfront_porch = t->vback_porch = 0; 4432 vm->vfront_porch = vm->vback_porch = 0;
4433 4433
4434 return true; 4434 return true;
4435} 4435}
@@ -4480,7 +4480,7 @@ static bool dsi_cm_calc(struct dsi_data *dsi,
4480 * especially as we go to LP between each pixel packet due to HW 4480 * especially as we go to LP between each pixel packet due to HW
4481 * "feature". So let's just estimate very roughly and multiply by 1.5. 4481 * "feature". So let's just estimate very roughly and multiply by 1.5.
4482 */ 4482 */
4483 pck = cfg->timings->pixelclock; 4483 pck = cfg->vm->pixelclock;
4484 pck = pck * 3 / 2; 4484 pck = pck * 3 / 2;
4485 txbyteclk = pck * bitspp / 8 / ndl; 4485 txbyteclk = pck * bitspp / 8 / ndl;
4486 4486
@@ -4522,7 +4522,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4522 4522
4523 dsi_tput = (u64)byteclk * ndl * 8; 4523 dsi_tput = (u64)byteclk * ndl * 8;
4524 4524
4525 req_vm = cfg->timings; 4525 req_vm = cfg->vm;
4526 req_pck_min = ctx->req_pck_min; 4526 req_pck_min = ctx->req_pck_min;
4527 req_pck_max = ctx->req_pck_max; 4527 req_pck_max = ctx->req_pck_max;
4528 req_pck_nom = ctx->req_pck_nom; 4528 req_pck_nom = ctx->req_pck_nom;
@@ -4656,7 +4656,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4656 4656
4657 /* setup DISPC videomode */ 4657 /* setup DISPC videomode */
4658 4658
4659 dispc_vm = &ctx->dispc_vm; 4659 dispc_vm = &ctx->vm;
4660 *dispc_vm = *req_vm; 4660 *dispc_vm = *req_vm;
4661 dispc_vm->pixelclock = dispc_pck; 4661 dispc_vm->pixelclock = dispc_pck;
4662 4662
@@ -4713,9 +4713,9 @@ static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4713 return false; 4713 return false;
4714 4714
4715#ifdef PRINT_VERBOSE_VM_TIMINGS 4715#ifdef PRINT_VERBOSE_VM_TIMINGS
4716 print_dispc_vm("dispc", &ctx->dispc_vm); 4716 print_dispc_vm("dispc", &ctx->vm);
4717 print_dsi_vm("dsi ", &ctx->dsi_vm); 4717 print_dsi_vm("dsi ", &ctx->dsi_vm);
4718 print_dispc_vm("req ", ctx->config->timings); 4718 print_dispc_vm("req ", ctx->config->vm);
4719 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4719 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4720#endif 4720#endif
4721 4721
@@ -4764,7 +4764,7 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4764 const struct omap_dss_dsi_config *cfg, 4764 const struct omap_dss_dsi_config *cfg,
4765 struct dsi_clk_calc_ctx *ctx) 4765 struct dsi_clk_calc_ctx *ctx)
4766{ 4766{
4767 const struct videomode *t = cfg->timings; 4767 const struct videomode *vm = cfg->vm;
4768 unsigned long clkin; 4768 unsigned long clkin;
4769 unsigned long pll_min; 4769 unsigned long pll_min;
4770 unsigned long pll_max; 4770 unsigned long pll_max;
@@ -4780,9 +4780,9 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4780 ctx->config = cfg; 4780 ctx->config = cfg;
4781 4781
4782 /* these limits should come from the panel driver */ 4782 /* these limits should come from the panel driver */
4783 ctx->req_pck_min = t->pixelclock - 1000; 4783 ctx->req_pck_min = vm->pixelclock - 1000;
4784 ctx->req_pck_nom = t->pixelclock; 4784 ctx->req_pck_nom = vm->pixelclock;
4785 ctx->req_pck_max = t->pixelclock + 1000; 4785 ctx->req_pck_max = vm->pixelclock + 1000;
4786 4786
4787 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4787 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4788 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4788 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
@@ -4839,7 +4839,7 @@ static int dsi_set_config(struct omap_dss_device *dssdev,
4839 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4839 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4840 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4840 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4841 4841
4842 dsi->timings = ctx.dispc_vm; 4842 dsi->vm = ctx.vm;
4843 dsi->vm_timings = ctx.dsi_vm; 4843 dsi->vm_timings = ctx.dsi_vm;
4844 4844
4845 mutex_unlock(&dsi->lock); 4845 mutex_unlock(&dsi->lock);
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index 384267591b12..56493b290731 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -366,8 +366,7 @@ bool dispc_div_calc(unsigned long dispc,
366 unsigned long pck_min, unsigned long pck_max, 366 unsigned long pck_min, unsigned long pck_max,
367 dispc_div_calc_func func, void *data); 367 dispc_div_calc_func func, void *data);
368 368
369bool dispc_mgr_timings_ok(enum omap_channel channel, 369bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm);
370 const struct videomode *timings);
371int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 370int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
372 struct dispc_clock_info *cinfo); 371 struct dispc_clock_info *cinfo);
373 372
@@ -390,7 +389,7 @@ void dispc_wb_enable(bool enable);
390bool dispc_wb_is_enabled(void); 389bool dispc_wb_is_enabled(void);
391void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 390void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
392int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 391int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
393 bool mem_to_mem, const struct videomode *timings); 392 bool mem_to_mem, const struct videomode *vm);
394 393
395/* VENC */ 394/* VENC */
396int venc_init_platform_driver(void) __init; 395int venc_init_platform_driver(void) __init;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi.h b/drivers/gpu/drm/omapdrm/dss/hdmi.h
index b97ee6702e6f..fb6cccd02374 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi.h
@@ -181,7 +181,7 @@ struct hdmi_video_format {
181}; 181};
182 182
183struct hdmi_config { 183struct hdmi_config {
184 struct videomode timings; 184 struct videomode vm;
185 struct hdmi_avi_infoframe infoframe; 185 struct hdmi_avi_infoframe infoframe;
186 enum hdmi_core_hdmi_dvi hdmi_dvi_mode; 186 enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
187}; 187};
@@ -298,11 +298,11 @@ int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
298void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, 298void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
299 struct hdmi_video_format *video_fmt); 299 struct hdmi_video_format *video_fmt);
300void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 300void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
301 struct videomode *timings); 301 struct videomode *vm);
302void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 302void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
303 struct videomode *timings); 303 struct videomode *vm);
304void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 304void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
305 struct videomode *timings, struct hdmi_config *param); 305 struct videomode *vm, struct hdmi_config *param);
306int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); 306int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
307phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); 307phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
308 308
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index a53dfd0bc3b3..e7162c16de2e 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -155,7 +155,7 @@ static void hdmi_power_off_core(struct omap_dss_device *dssdev)
155static int hdmi_power_on_full(struct omap_dss_device *dssdev) 155static int hdmi_power_on_full(struct omap_dss_device *dssdev)
156{ 156{
157 int r; 157 int r;
158 struct videomode *p; 158 struct videomode *vm;
159 enum omap_channel channel = dssdev->dispc_channel; 159 enum omap_channel channel = dssdev->dispc_channel;
160 struct hdmi_wp_data *wp = &hdmi.wp; 160 struct hdmi_wp_data *wp = &hdmi.wp;
161 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 161 struct dss_pll_clock_info hdmi_cinfo = { 0 };
@@ -169,13 +169,13 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
169 hdmi_wp_clear_irqenable(wp, 0xffffffff); 169 hdmi_wp_clear_irqenable(wp, 0xffffffff);
170 hdmi_wp_set_irqstatus(wp, 0xffffffff); 170 hdmi_wp_set_irqstatus(wp, 0xffffffff);
171 171
172 p = &hdmi.cfg.timings; 172 vm = &hdmi.cfg.vm;
173 173
174 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", p->hactive, 174 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
175 p->vactive); 175 vm->vactive);
176 176
177 pc = p->pixelclock; 177 pc = vm->pixelclock;
178 if (p->flags & DISPLAY_FLAGS_DOUBLECLK) 178 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
179 pc *= 2; 179 pc *= 2;
180 180
181 /* DSS_HDMI_TCLK is bitclk / 10 */ 181 /* DSS_HDMI_TCLK is bitclk / 10 */
@@ -210,7 +210,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
210 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 210 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
211 211
212 /* tv size */ 212 /* tv size */
213 dss_mgr_set_timings(channel, p); 213 dss_mgr_set_timings(channel, vm);
214 214
215 r = dss_mgr_enable(channel); 215 r = dss_mgr_enable(channel);
216 if (r) 216 if (r)
@@ -256,30 +256,30 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
256} 256}
257 257
258static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 258static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
259 struct videomode *timings) 259 struct videomode *vm)
260{ 260{
261 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) 261 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
262 return -EINVAL; 262 return -EINVAL;
263 263
264 return 0; 264 return 0;
265} 265}
266 266
267static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 267static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
268 struct videomode *timings) 268 struct videomode *vm)
269{ 269{
270 mutex_lock(&hdmi.lock); 270 mutex_lock(&hdmi.lock);
271 271
272 hdmi.cfg.timings = *timings; 272 hdmi.cfg.vm = *vm;
273 273
274 dispc_set_tv_pclk(timings->pixelclock); 274 dispc_set_tv_pclk(vm->pixelclock);
275 275
276 mutex_unlock(&hdmi.lock); 276 mutex_unlock(&hdmi.lock);
277} 277}
278 278
279static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 279static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
280 struct videomode *timings) 280 struct videomode *vm)
281{ 281{
282 *timings = hdmi.cfg.timings; 282 *vm = hdmi.cfg.vm;
283} 283}
284 284
285static void hdmi_dump_regs(struct seq_file *s) 285static void hdmi_dump_regs(struct seq_file *s)
@@ -353,7 +353,7 @@ static int hdmi_display_enable(struct omap_dss_device *dssdev)
353 353
354 if (hdmi.audio_configured) { 354 if (hdmi.audio_configured) {
355 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 355 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
356 hdmi.cfg.timings.pixelclock); 356 hdmi.cfg.vm.pixelclock);
357 if (r) { 357 if (r) {
358 DSSERR("Error restoring audio configuration: %d", r); 358 DSSERR("Error restoring audio configuration: %d", r);
359 hdmi.audio_abort_cb(&hdmi.pdev->dev); 359 hdmi.audio_abort_cb(&hdmi.pdev->dev);
@@ -644,7 +644,7 @@ static int hdmi_audio_config(struct device *dev,
644 } 644 }
645 645
646 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, 646 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
647 hd->cfg.timings.pixelclock); 647 hd->cfg.vm.pixelclock);
648 if (!ret) { 648 if (!ret) {
649 hd->audio_configured = true; 649 hd->audio_configured = true;
650 hd->audio_config = *dss_audio; 650 hd->audio_config = *dss_audio;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
index 505cfee892aa..e05b7ac4f7dd 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.c
@@ -310,7 +310,7 @@ void hdmi4_configure(struct hdmi_core_data *core,
310 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 310 struct hdmi_wp_data *wp, struct hdmi_config *cfg)
311{ 311{
312 /* HDMI */ 312 /* HDMI */
313 struct videomode video_timing; 313 struct videomode vm;
314 struct hdmi_video_format video_format; 314 struct hdmi_video_format video_format;
315 /* HDMI core */ 315 /* HDMI core */
316 struct hdmi_core_video_config v_core_cfg; 316 struct hdmi_core_video_config v_core_cfg;
@@ -318,16 +318,16 @@ void hdmi4_configure(struct hdmi_core_data *core,
318 318
319 hdmi_core_init(&v_core_cfg); 319 hdmi_core_init(&v_core_cfg);
320 320
321 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 321 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
322 322
323 hdmi_wp_video_config_timing(wp, &video_timing); 323 hdmi_wp_video_config_timing(wp, &vm);
324 324
325 /* video config */ 325 /* video config */
326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
327 327
328 hdmi_wp_video_config_format(wp, &video_format); 328 hdmi_wp_video_config_format(wp, &video_format);
329 329
330 hdmi_wp_video_config_interface(wp, &video_timing); 330 hdmi_wp_video_config_interface(wp, &vm);
331 331
332 /* 332 /*
333 * configure core video part 333 * configure core video part
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index 880f67ae6e9b..678dfb02764a 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -172,7 +172,7 @@ static void hdmi_power_off_core(struct omap_dss_device *dssdev)
172static int hdmi_power_on_full(struct omap_dss_device *dssdev) 172static int hdmi_power_on_full(struct omap_dss_device *dssdev)
173{ 173{
174 int r; 174 int r;
175 struct videomode *p; 175 struct videomode *vm;
176 enum omap_channel channel = dssdev->dispc_channel; 176 enum omap_channel channel = dssdev->dispc_channel;
177 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 177 struct dss_pll_clock_info hdmi_cinfo = { 0 };
178 unsigned pc; 178 unsigned pc;
@@ -181,13 +181,13 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
181 if (r) 181 if (r)
182 return r; 182 return r;
183 183
184 p = &hdmi.cfg.timings; 184 vm = &hdmi.cfg.vm;
185 185
186 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", p->hactive, 186 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
187 p->vactive); 187 vm->vactive);
188 188
189 pc = p->pixelclock; 189 pc = vm->pixelclock;
190 if (p->flags & DISPLAY_FLAGS_DOUBLECLK) 190 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
191 pc *= 2; 191 pc *= 2;
192 192
193 /* DSS_HDMI_TCLK is bitclk / 10 */ 193 /* DSS_HDMI_TCLK is bitclk / 10 */
@@ -227,7 +227,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
227 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 227 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
228 228
229 /* tv size */ 229 /* tv size */
230 dss_mgr_set_timings(channel, p); 230 dss_mgr_set_timings(channel, vm);
231 231
232 r = dss_mgr_enable(channel); 232 r = dss_mgr_enable(channel);
233 if (r) 233 if (r)
@@ -273,30 +273,30 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
273} 273}
274 274
275static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 275static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
276 struct videomode *timings) 276 struct videomode *vm)
277{ 277{
278 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings)) 278 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
279 return -EINVAL; 279 return -EINVAL;
280 280
281 return 0; 281 return 0;
282} 282}
283 283
284static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 284static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
285 struct videomode *timings) 285 struct videomode *vm)
286{ 286{
287 mutex_lock(&hdmi.lock); 287 mutex_lock(&hdmi.lock);
288 288
289 hdmi.cfg.timings = *timings; 289 hdmi.cfg.vm = *vm;
290 290
291 dispc_set_tv_pclk(timings->pixelclock); 291 dispc_set_tv_pclk(vm->pixelclock);
292 292
293 mutex_unlock(&hdmi.lock); 293 mutex_unlock(&hdmi.lock);
294} 294}
295 295
296static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 296static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
297 struct videomode *timings) 297 struct videomode *vm)
298{ 298{
299 *timings = hdmi.cfg.timings; 299 *vm = hdmi.cfg.vm;
300} 300}
301 301
302static void hdmi_dump_regs(struct seq_file *s) 302static void hdmi_dump_regs(struct seq_file *s)
@@ -379,7 +379,7 @@ static int hdmi_display_enable(struct omap_dss_device *dssdev)
379 379
380 if (hdmi.audio_configured) { 380 if (hdmi.audio_configured) {
381 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 381 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
382 hdmi.cfg.timings.pixelclock); 382 hdmi.cfg.vm.pixelclock);
383 if (r) { 383 if (r) {
384 DSSERR("Error restoring audio configuration: %d", r); 384 DSSERR("Error restoring audio configuration: %d", r);
385 hdmi.audio_abort_cb(&hdmi.pdev->dev); 385 hdmi.audio_abort_cb(&hdmi.pdev->dev);
@@ -670,7 +670,7 @@ static int hdmi_audio_config(struct device *dev,
670 } 670 }
671 671
672 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, 672 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
673 hd->cfg.timings.pixelclock); 673 hd->cfg.vm.pixelclock);
674 674
675 if (!ret) { 675 if (!ret) {
676 hd->audio_configured = true; 676 hd->audio_configured = true;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index a5ac9318a11d..8de1d7b2ae55 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -292,35 +292,35 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
292{ 292{
293 DSSDBG("hdmi_core_init\n"); 293 DSSDBG("hdmi_core_init\n");
294 294
295 video_cfg->v_fc_config.timings = cfg->timings; 295 video_cfg->v_fc_config.vm = cfg->vm;
296 296
297 /* video core */ 297 /* video core */
298 video_cfg->data_enable_pol = 1; /* It is always 1*/ 298 video_cfg->data_enable_pol = 1; /* It is always 1*/
299 video_cfg->hblank = cfg->timings.hfront_porch + 299 video_cfg->hblank = cfg->vm.hfront_porch +
300 cfg->timings.hback_porch + cfg->timings.hsync_len; 300 cfg->vm.hback_porch + cfg->vm.hsync_len;
301 video_cfg->vblank_osc = 0; 301 video_cfg->vblank_osc = 0;
302 video_cfg->vblank = cfg->timings.vsync_len + cfg->timings.vfront_porch + 302 video_cfg->vblank = cfg->vm.vsync_len + cfg->vm.vfront_porch +
303 cfg->timings.vback_porch; 303 cfg->vm.vback_porch;
304 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; 304 video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
305 305
306 if (cfg->timings.flags & DISPLAY_FLAGS_INTERLACED) { 306 if (cfg->vm.flags & DISPLAY_FLAGS_INTERLACED) {
307 /* set vblank_osc if vblank is fractional */ 307 /* set vblank_osc if vblank is fractional */
308 if (video_cfg->vblank % 2 != 0) 308 if (video_cfg->vblank % 2 != 0)
309 video_cfg->vblank_osc = 1; 309 video_cfg->vblank_osc = 1;
310 310
311 video_cfg->v_fc_config.timings.vactive /= 2; 311 video_cfg->v_fc_config.vm.vactive /= 2;
312 video_cfg->vblank /= 2; 312 video_cfg->vblank /= 2;
313 video_cfg->v_fc_config.timings.vfront_porch /= 2; 313 video_cfg->v_fc_config.vm.vfront_porch /= 2;
314 video_cfg->v_fc_config.timings.vsync_len /= 2; 314 video_cfg->v_fc_config.vm.vsync_len /= 2;
315 video_cfg->v_fc_config.timings.vback_porch /= 2; 315 video_cfg->v_fc_config.vm.vback_porch /= 2;
316 } 316 }
317 317
318 if (cfg->timings.flags & DISPLAY_FLAGS_DOUBLECLK) { 318 if (cfg->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
319 video_cfg->v_fc_config.timings.hactive *= 2; 319 video_cfg->v_fc_config.vm.hactive *= 2;
320 video_cfg->hblank *= 2; 320 video_cfg->hblank *= 2;
321 video_cfg->v_fc_config.timings.hfront_porch *= 2; 321 video_cfg->v_fc_config.vm.hfront_porch *= 2;
322 video_cfg->v_fc_config.timings.hsync_len *= 2; 322 video_cfg->v_fc_config.vm.hsync_len *= 2;
323 video_cfg->v_fc_config.timings.hback_porch *= 2; 323 video_cfg->v_fc_config.vm.hback_porch *= 2;
324 } 324 }
325} 325}
326 326
@@ -329,12 +329,12 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
329 struct hdmi_core_vid_config *cfg) 329 struct hdmi_core_vid_config *cfg)
330{ 330{
331 void __iomem *base = core->base; 331 void __iomem *base = core->base;
332 struct videomode *ovt = &cfg->v_fc_config.timings; 332 struct videomode *vm = &cfg->v_fc_config.vm;
333 unsigned char r = 0; 333 unsigned char r = 0;
334 bool vsync_pol, hsync_pol; 334 bool vsync_pol, hsync_pol;
335 335
336 vsync_pol = !!(ovt->flags & DISPLAY_FLAGS_VSYNC_HIGH); 336 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
337 hsync_pol = !!(ovt->flags & DISPLAY_FLAGS_HSYNC_HIGH); 337 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
338 338
339 /* Set hsync, vsync and data-enable polarity */ 339 /* Set hsync, vsync and data-enable polarity */
340 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); 340 r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
@@ -342,16 +342,16 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
342 r = FLD_MOD(r, hsync_pol, 5, 5); 342 r = FLD_MOD(r, hsync_pol, 5, 5);
343 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4); 343 r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
344 r = FLD_MOD(r, cfg->vblank_osc, 1, 1); 344 r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
345 r = FLD_MOD(r, !!(ovt->flags & DISPLAY_FLAGS_INTERLACED), 0, 0); 345 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 0, 0);
346 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r); 346 hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
347 347
348 /* set x resolution */ 348 /* set x resolution */
349 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, ovt->hactive >> 8, 4, 0); 349 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0);
350 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, ovt->hactive & 0xFF, 7, 0); 350 REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0);
351 351
352 /* set y resolution */ 352 /* set y resolution */
353 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, ovt->vactive >> 8, 4, 0); 353 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0);
354 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, ovt->vactive & 0xFF, 7, 0); 354 REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0);
355 355
356 /* set horizontal blanking pixels */ 356 /* set horizontal blanking pixels */
357 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); 357 REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
@@ -361,28 +361,28 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
361 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); 361 REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
362 362
363 /* set horizontal sync offset */ 363 /* set horizontal sync offset */
364 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, ovt->hfront_porch >> 8, 364 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8,
365 4, 0); 365 4, 0);
366 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, ovt->hfront_porch & 0xFF, 366 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF,
367 7, 0); 367 7, 0);
368 368
369 /* set vertical sync offset */ 369 /* set vertical sync offset */
370 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, ovt->vfront_porch, 7, 0); 370 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0);
371 371
372 /* set horizontal sync pulse width */ 372 /* set horizontal sync pulse width */
373 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (ovt->hsync_len >> 8), 373 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8),
374 1, 0); 374 1, 0);
375 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, ovt->hsync_len & 0xFF, 375 REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF,
376 7, 0); 376 7, 0);
377 377
378 /* set vertical sync pulse width */ 378 /* set vertical sync pulse width */
379 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, ovt->vsync_len, 5, 0); 379 REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0);
380 380
381 /* select DVI mode */ 381 /* select DVI mode */
382 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, 382 REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
383 cfg->v_fc_config.hdmi_dvi_mode, 3, 3); 383 cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
384 384
385 if (ovt->flags & DISPLAY_FLAGS_DOUBLECLK) 385 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
386 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); 386 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4);
387 else 387 else
388 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); 388 REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4);
@@ -609,7 +609,7 @@ int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
609void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 609void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
610 struct hdmi_config *cfg) 610 struct hdmi_config *cfg)
611{ 611{
612 struct videomode video_timing; 612 struct videomode vm;
613 struct hdmi_video_format video_format; 613 struct hdmi_video_format video_format;
614 struct hdmi_core_vid_config v_core_cfg; 614 struct hdmi_core_vid_config v_core_cfg;
615 615
@@ -617,16 +617,16 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
617 617
618 hdmi_core_init(&v_core_cfg, cfg); 618 hdmi_core_init(&v_core_cfg, cfg);
619 619
620 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 620 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg);
621 621
622 hdmi_wp_video_config_timing(wp, &video_timing); 622 hdmi_wp_video_config_timing(wp, &vm);
623 623
624 /* video config */ 624 /* video config */
625 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 625 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
626 626
627 hdmi_wp_video_config_format(wp, &video_format); 627 hdmi_wp_video_config_format(wp, &video_format);
628 628
629 hdmi_wp_video_config_interface(wp, &video_timing); 629 hdmi_wp_video_config_interface(wp, &vm);
630 630
631 /* support limited range with 24 bit color depth for now */ 631 /* support limited range with 24 bit color depth for now */
632 hdmi_core_configure_range(core); 632 hdmi_core_configure_range(core);
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index b490e335b3df..b783d5a0750e 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -144,25 +144,25 @@ void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
144} 144}
145 145
146void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 146void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
147 struct videomode *timings) 147 struct videomode *vm)
148{ 148{
149 u32 r; 149 u32 r;
150 bool vsync_pol, hsync_pol; 150 bool vsync_pol, hsync_pol;
151 DSSDBG("Enter hdmi_wp_video_config_interface\n"); 151 DSSDBG("Enter hdmi_wp_video_config_interface\n");
152 152
153 vsync_pol = !!(timings->flags & DISPLAY_FLAGS_VSYNC_HIGH); 153 vsync_pol = !!(vm->flags & DISPLAY_FLAGS_VSYNC_HIGH);
154 hsync_pol = !!(timings->flags & DISPLAY_FLAGS_HSYNC_HIGH); 154 hsync_pol = !!(vm->flags & DISPLAY_FLAGS_HSYNC_HIGH);
155 155
156 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); 156 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
157 r = FLD_MOD(r, vsync_pol, 7, 7); 157 r = FLD_MOD(r, vsync_pol, 7, 7);
158 r = FLD_MOD(r, hsync_pol, 6, 6); 158 r = FLD_MOD(r, hsync_pol, 6, 6);
159 r = FLD_MOD(r, !!(timings->flags & DISPLAY_FLAGS_INTERLACED), 3, 3); 159 r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);
160 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ 160 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
161 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); 161 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
162} 162}
163 163
164void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 164void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
165 struct videomode *timings) 165 struct videomode *vm)
166{ 166{
167 u32 timing_h = 0; 167 u32 timing_h = 0;
168 u32 timing_v = 0; 168 u32 timing_v = 0;
@@ -181,47 +181,47 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
181 omapdss_get_version() == OMAPDSS_VER_OMAP4) 181 omapdss_get_version() == OMAPDSS_VER_OMAP4)
182 hsync_len_offset = 0; 182 hsync_len_offset = 0;
183 183
184 timing_h |= FLD_VAL(timings->hback_porch, 31, 20); 184 timing_h |= FLD_VAL(vm->hback_porch, 31, 20);
185 timing_h |= FLD_VAL(timings->hfront_porch, 19, 8); 185 timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);
186 timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0); 186 timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);
187 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); 187 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
188 188
189 timing_v |= FLD_VAL(timings->vback_porch, 31, 20); 189 timing_v |= FLD_VAL(vm->vback_porch, 31, 20);
190 timing_v |= FLD_VAL(timings->vfront_porch, 19, 8); 190 timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);
191 timing_v |= FLD_VAL(timings->vsync_len, 7, 0); 191 timing_v |= FLD_VAL(vm->vsync_len, 7, 0);
192 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); 192 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
193} 193}
194 194
195void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 195void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
196 struct videomode *timings, struct hdmi_config *param) 196 struct videomode *vm, struct hdmi_config *param)
197{ 197{
198 DSSDBG("Enter hdmi_wp_video_init_format\n"); 198 DSSDBG("Enter hdmi_wp_video_init_format\n");
199 199
200 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; 200 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
201 video_fmt->y_res = param->timings.vactive; 201 video_fmt->y_res = param->vm.vactive;
202 video_fmt->x_res = param->timings.hactive; 202 video_fmt->x_res = param->vm.hactive;
203 203
204 timings->hback_porch = param->timings.hback_porch; 204 vm->hback_porch = param->vm.hback_porch;
205 timings->hfront_porch = param->timings.hfront_porch; 205 vm->hfront_porch = param->vm.hfront_porch;
206 timings->hsync_len = param->timings.hsync_len; 206 vm->hsync_len = param->vm.hsync_len;
207 timings->vback_porch = param->timings.vback_porch; 207 vm->vback_porch = param->vm.vback_porch;
208 timings->vfront_porch = param->timings.vfront_porch; 208 vm->vfront_porch = param->vm.vfront_porch;
209 timings->vsync_len = param->timings.vsync_len; 209 vm->vsync_len = param->vm.vsync_len;
210 210
211 timings->flags = param->timings.flags; 211 vm->flags = param->vm.flags;
212 212
213 if (param->timings.flags & DISPLAY_FLAGS_INTERLACED) { 213 if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {
214 video_fmt->y_res /= 2; 214 video_fmt->y_res /= 2;
215 timings->vback_porch /= 2; 215 vm->vback_porch /= 2;
216 timings->vfront_porch /= 2; 216 vm->vfront_porch /= 2;
217 timings->vsync_len /= 2; 217 vm->vsync_len /= 2;
218 } 218 }
219 219
220 if (param->timings.flags & DISPLAY_FLAGS_DOUBLECLK) { 220 if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {
221 video_fmt->x_res *= 2; 221 video_fmt->x_res *= 2;
222 timings->hfront_porch *= 2; 222 vm->hfront_porch *= 2;
223 timings->hsync_len *= 2; 223 vm->hsync_len *= 2;
224 timings->hback_porch *= 2; 224 vm->hback_porch *= 2;
225 } 225 }
226} 226}
227 227
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 54e88ee3ef8e..b420dde8c0fb 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -290,7 +290,7 @@ struct omap_dss_dsi_videomode_timings {
290struct omap_dss_dsi_config { 290struct omap_dss_dsi_config {
291 enum omap_dss_dsi_mode mode; 291 enum omap_dss_dsi_mode mode;
292 enum omap_dss_dsi_pixel_format pixel_format; 292 enum omap_dss_dsi_pixel_format pixel_format;
293 const struct videomode *timings; 293 const struct videomode *vm;
294 294
295 unsigned long hs_clk_min, hs_clk_max; 295 unsigned long hs_clk_min, hs_clk_max;
296 unsigned long lp_clk_min, lp_clk_max; 296 unsigned long lp_clk_min, lp_clk_max;
@@ -299,12 +299,12 @@ struct omap_dss_dsi_config {
299 enum omap_dss_dsi_trans_mode trans_mode; 299 enum omap_dss_dsi_trans_mode trans_mode;
300}; 300};
301 301
302/* Hardcoded timings for tv modes. Venc only uses these to 302/* Hardcoded videomodes for tv. Venc only uses these to
303 * identify the mode, and does not actually use the configs 303 * identify the mode, and does not actually use the configs
304 * itself. However, the configs should be something that 304 * itself. However, the configs should be something that
305 * a normal monitor can also show */ 305 * a normal monitor can also show */
306extern const struct videomode omap_dss_pal_timings; 306extern const struct videomode omap_dss_pal_vm;
307extern const struct videomode omap_dss_ntsc_timings; 307extern const struct videomode omap_dss_ntsc_vm;
308 308
309struct omap_dss_cpr_coefs { 309struct omap_dss_cpr_coefs {
310 s16 rr, rg, rb; 310 s16 rr, rg, rb;
@@ -466,11 +466,11 @@ struct omapdss_dpi_ops {
466 void (*disable)(struct omap_dss_device *dssdev); 466 void (*disable)(struct omap_dss_device *dssdev);
467 467
468 int (*check_timings)(struct omap_dss_device *dssdev, 468 int (*check_timings)(struct omap_dss_device *dssdev,
469 struct videomode *timings); 469 struct videomode *vm);
470 void (*set_timings)(struct omap_dss_device *dssdev, 470 void (*set_timings)(struct omap_dss_device *dssdev,
471 struct videomode *timings); 471 struct videomode *vm);
472 void (*get_timings)(struct omap_dss_device *dssdev, 472 void (*get_timings)(struct omap_dss_device *dssdev,
473 struct videomode *timings); 473 struct videomode *vm);
474 474
475 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); 475 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
476}; 476};
@@ -485,11 +485,11 @@ struct omapdss_sdi_ops {
485 void (*disable)(struct omap_dss_device *dssdev); 485 void (*disable)(struct omap_dss_device *dssdev);
486 486
487 int (*check_timings)(struct omap_dss_device *dssdev, 487 int (*check_timings)(struct omap_dss_device *dssdev,
488 struct videomode *timings); 488 struct videomode *vm);
489 void (*set_timings)(struct omap_dss_device *dssdev, 489 void (*set_timings)(struct omap_dss_device *dssdev,
490 struct videomode *timings); 490 struct videomode *vm);
491 void (*get_timings)(struct omap_dss_device *dssdev, 491 void (*get_timings)(struct omap_dss_device *dssdev,
492 struct videomode *timings); 492 struct videomode *vm);
493 493
494 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); 494 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
495}; 495};
@@ -504,11 +504,11 @@ struct omapdss_dvi_ops {
504 void (*disable)(struct omap_dss_device *dssdev); 504 void (*disable)(struct omap_dss_device *dssdev);
505 505
506 int (*check_timings)(struct omap_dss_device *dssdev, 506 int (*check_timings)(struct omap_dss_device *dssdev,
507 struct videomode *timings); 507 struct videomode *vm);
508 void (*set_timings)(struct omap_dss_device *dssdev, 508 void (*set_timings)(struct omap_dss_device *dssdev,
509 struct videomode *timings); 509 struct videomode *vm);
510 void (*get_timings)(struct omap_dss_device *dssdev, 510 void (*get_timings)(struct omap_dss_device *dssdev,
511 struct videomode *timings); 511 struct videomode *vm);
512}; 512};
513 513
514struct omapdss_atv_ops { 514struct omapdss_atv_ops {
@@ -521,11 +521,11 @@ struct omapdss_atv_ops {
521 void (*disable)(struct omap_dss_device *dssdev); 521 void (*disable)(struct omap_dss_device *dssdev);
522 522
523 int (*check_timings)(struct omap_dss_device *dssdev, 523 int (*check_timings)(struct omap_dss_device *dssdev,
524 struct videomode *timings); 524 struct videomode *vm);
525 void (*set_timings)(struct omap_dss_device *dssdev, 525 void (*set_timings)(struct omap_dss_device *dssdev,
526 struct videomode *timings); 526 struct videomode *vm);
527 void (*get_timings)(struct omap_dss_device *dssdev, 527 void (*get_timings)(struct omap_dss_device *dssdev,
528 struct videomode *timings); 528 struct videomode *vm);
529 529
530 void (*set_type)(struct omap_dss_device *dssdev, 530 void (*set_type)(struct omap_dss_device *dssdev,
531 enum omap_dss_venc_type type); 531 enum omap_dss_venc_type type);
@@ -546,11 +546,11 @@ struct omapdss_hdmi_ops {
546 void (*disable)(struct omap_dss_device *dssdev); 546 void (*disable)(struct omap_dss_device *dssdev);
547 547
548 int (*check_timings)(struct omap_dss_device *dssdev, 548 int (*check_timings)(struct omap_dss_device *dssdev,
549 struct videomode *timings); 549 struct videomode *vm);
550 void (*set_timings)(struct omap_dss_device *dssdev, 550 void (*set_timings)(struct omap_dss_device *dssdev,
551 struct videomode *timings); 551 struct videomode *vm);
552 void (*get_timings)(struct omap_dss_device *dssdev, 552 void (*get_timings)(struct omap_dss_device *dssdev,
553 struct videomode *timings); 553 struct videomode *vm);
554 554
555 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); 555 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
556 bool (*detect)(struct omap_dss_device *dssdev); 556 bool (*detect)(struct omap_dss_device *dssdev);
@@ -656,7 +656,7 @@ struct omap_dss_device {
656 } phy; 656 } phy;
657 657
658 struct { 658 struct {
659 struct videomode timings; 659 struct videomode vm;
660 660
661 enum omap_dss_dsi_pixel_format dsi_pix_fmt; 661 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
662 enum omap_dss_dsi_mode dsi_mode; 662 enum omap_dss_dsi_mode dsi_mode;
@@ -749,11 +749,11 @@ struct omap_dss_driver {
749 int (*get_recommended_bpp)(struct omap_dss_device *dssdev); 749 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
750 750
751 int (*check_timings)(struct omap_dss_device *dssdev, 751 int (*check_timings)(struct omap_dss_device *dssdev,
752 struct videomode *timings); 752 struct videomode *vm);
753 void (*set_timings)(struct omap_dss_device *dssdev, 753 void (*set_timings)(struct omap_dss_device *dssdev,
754 struct videomode *timings); 754 struct videomode *vm);
755 void (*get_timings)(struct omap_dss_device *dssdev, 755 void (*get_timings)(struct omap_dss_device *dssdev,
756 struct videomode *timings); 756 struct videomode *vm);
757 757
758 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); 758 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
759 u32 (*get_wss)(struct omap_dss_device *dssdev); 759 u32 (*get_wss)(struct omap_dss_device *dssdev);
@@ -811,7 +811,7 @@ void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
811 u16 *xres, u16 *yres); 811 u16 *xres, u16 *yres);
812int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); 812int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
813void omapdss_default_get_timings(struct omap_dss_device *dssdev, 813void omapdss_default_get_timings(struct omap_dss_device *dssdev,
814 struct videomode *timings); 814 struct videomode *vm);
815 815
816typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 816typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
817int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 817int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
@@ -865,7 +865,7 @@ void dispc_mgr_go(enum omap_channel channel);
865void dispc_mgr_set_lcd_config(enum omap_channel channel, 865void dispc_mgr_set_lcd_config(enum omap_channel channel,
866 const struct dss_lcd_mgr_config *config); 866 const struct dss_lcd_mgr_config *config);
867void dispc_mgr_set_timings(enum omap_channel channel, 867void dispc_mgr_set_timings(enum omap_channel channel,
868 const struct videomode *timings); 868 const struct videomode *vm);
869void dispc_mgr_setup(enum omap_channel channel, 869void dispc_mgr_setup(enum omap_channel channel,
870 const struct omap_overlay_manager_info *info); 870 const struct omap_overlay_manager_info *info);
871u32 dispc_mgr_gamma_size(enum omap_channel channel); 871u32 dispc_mgr_gamma_size(enum omap_channel channel);
@@ -878,8 +878,7 @@ bool dispc_ovl_enabled(enum omap_plane plane);
878void dispc_ovl_set_channel_out(enum omap_plane plane, 878void dispc_ovl_set_channel_out(enum omap_plane plane,
879 enum omap_channel channel); 879 enum omap_channel channel);
880int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, 880int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
881 bool replication, const struct videomode *mgr_timings, 881 bool replication, const struct videomode *vm, bool mem_to_mem);
882 bool mem_to_mem);
883 882
884enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel); 883enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel);
885 884
@@ -893,7 +892,7 @@ struct dss_mgr_ops {
893 int (*enable)(enum omap_channel channel); 892 int (*enable)(enum omap_channel channel);
894 void (*disable)(enum omap_channel channel); 893 void (*disable)(enum omap_channel channel);
895 void (*set_timings)(enum omap_channel channel, 894 void (*set_timings)(enum omap_channel channel,
896 const struct videomode *timings); 895 const struct videomode *vm);
897 void (*set_lcd_config)(enum omap_channel channel, 896 void (*set_lcd_config)(enum omap_channel channel,
898 const struct dss_lcd_mgr_config *config); 897 const struct dss_lcd_mgr_config *config);
899 int (*register_framedone_handler)(enum omap_channel channel, 898 int (*register_framedone_handler)(enum omap_channel channel,
@@ -910,7 +909,7 @@ int dss_mgr_connect(enum omap_channel channel,
910void dss_mgr_disconnect(enum omap_channel channel, 909void dss_mgr_disconnect(enum omap_channel channel,
911 struct omap_dss_device *dst); 910 struct omap_dss_device *dst);
912void dss_mgr_set_timings(enum omap_channel channel, 911void dss_mgr_set_timings(enum omap_channel channel,
913 const struct videomode *timings); 912 const struct videomode *vm);
914void dss_mgr_set_lcd_config(enum omap_channel channel, 913void dss_mgr_set_lcd_config(enum omap_channel channel,
915 const struct dss_lcd_mgr_config *config); 914 const struct dss_lcd_mgr_config *config);
916int dss_mgr_enable(enum omap_channel channel); 915int dss_mgr_enable(enum omap_channel channel);
diff --git a/drivers/gpu/drm/omapdrm/dss/output.c b/drivers/gpu/drm/omapdrm/dss/output.c
index 28fc5c159066..a901af5a9bc3 100644
--- a/drivers/gpu/drm/omapdrm/dss/output.c
+++ b/drivers/gpu/drm/omapdrm/dss/output.c
@@ -201,10 +201,9 @@ void dss_mgr_disconnect(enum omap_channel channel,
201} 201}
202EXPORT_SYMBOL(dss_mgr_disconnect); 202EXPORT_SYMBOL(dss_mgr_disconnect);
203 203
204void dss_mgr_set_timings(enum omap_channel channel, 204void dss_mgr_set_timings(enum omap_channel channel, const struct videomode *vm)
205 const struct videomode *timings)
206{ 205{
207 dss_mgr_ops->set_timings(channel, timings); 206 dss_mgr_ops->set_timings(channel, vm);
208} 207}
209EXPORT_SYMBOL(dss_mgr_set_timings); 208EXPORT_SYMBOL(dss_mgr_set_timings);
210 209
diff --git a/drivers/gpu/drm/omapdrm/dss/rfbi.c b/drivers/gpu/drm/omapdrm/dss/rfbi.c
index a08734ae2253..09724757366a 100644
--- a/drivers/gpu/drm/omapdrm/dss/rfbi.c
+++ b/drivers/gpu/drm/omapdrm/dss/rfbi.c
@@ -113,7 +113,7 @@ static struct {
113 113
114 struct semaphore bus_lock; 114 struct semaphore bus_lock;
115 115
116 struct videomode timings; 116 struct videomode vm;
117 int pixel_size; 117 int pixel_size;
118 int data_lines; 118 int data_lines;
119 struct rfbi_timings intf_timings; 119 struct rfbi_timings intf_timings;
@@ -308,15 +308,15 @@ static int rfbi_transfer_area(struct omap_dss_device *dssdev,
308 u32 l; 308 u32 l;
309 int r; 309 int r;
310 struct omap_overlay_manager *mgr = rfbi.output.manager; 310 struct omap_overlay_manager *mgr = rfbi.output.manager;
311 u16 width = rfbi.timings.hactive; 311 u16 width = rfbi.vm.hactive;
312 u16 height = rfbi.timings.vactive; 312 u16 height = rfbi.vm.vactive;
313 313
314 /*BUG_ON(callback == 0);*/ 314 /*BUG_ON(callback == 0);*/
315 BUG_ON(rfbi.framedone_callback != NULL); 315 BUG_ON(rfbi.framedone_callback != NULL);
316 316
317 DSSDBG("rfbi_transfer_area %dx%d\n", width, height); 317 DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
318 318
319 dss_mgr_set_timings(mgr, &rfbi.timings); 319 dss_mgr_set_timings(mgr, &rfbi.vm);
320 320
321 r = dss_mgr_enable(mgr); 321 r = dss_mgr_enable(mgr);
322 if (r) 322 if (r)
@@ -777,8 +777,8 @@ static int rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
777 777
778static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h) 778static void rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h)
779{ 779{
780 rfbi.timings.hactive = w; 780 rfbi.vm.hactive = w;
781 rfbi.timings.vactive = h; 781 rfbi.vm.vactive = h;
782} 782}
783 783
784static void rfbi_set_pixel_size(struct omap_dss_device *dssdev, int pixel_size) 784static void rfbi_set_pixel_size(struct omap_dss_device *dssdev, int pixel_size)
@@ -858,26 +858,26 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
858 * are expected to be already configured by the panel driver via 858 * are expected to be already configured by the panel driver via
859 * omapdss_rfbi_set_size() 859 * omapdss_rfbi_set_size()
860 */ 860 */
861 rfbi.timings.hsync_len = 1; 861 rfbi.vm.hsync_len = 1;
862 rfbi.timings.hfront_porch = 1; 862 rfbi.vm.hfront_porch = 1;
863 rfbi.timings.hback_porch = 1; 863 rfbi.vm.hback_porch = 1;
864 rfbi.timings.vsync_len = 1; 864 rfbi.vm.vsync_len = 1;
865 rfbi.timings.vfront_porch = 0; 865 rfbi.vm.vfront_porch = 0;
866 rfbi.timings.vback_porch = 0; 866 rfbi.vm.vback_porch = 0;
867 867
868 rfbi.timings.flags &= ~DISPLAY_FLAGS_INTERLACED; 868 rfbi.vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
869 rfbi.timings.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 869 rfbi.vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
870 rfbi.timings.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 870 rfbi.vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
871 rfbi.timings.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 871 rfbi.vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
872 rfbi.timings.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 872 rfbi.vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
873 rfbi.timings.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 873 rfbi.vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
874 rfbi.timings.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 874 rfbi.vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
875 rfbi.timings.flags &= ~DISPLAY_FLAGS_DE_LOW; 875 rfbi.vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
876 rfbi.timings.flags |= DISPLAY_FLAGS_DE_HIGH; 876 rfbi.vm.flags |= DISPLAY_FLAGS_DE_HIGH;
877 rfbi.timings.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 877 rfbi.vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
878 rfbi.timings.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 878 rfbi.vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
879 879
880 dss_mgr_set_timings(mgr, &rfbi.timings); 880 dss_mgr_set_timings(mgr, &rfbi.vm);
881} 881}
882 882
883static int rfbi_display_enable(struct omap_dss_device *dssdev) 883static int rfbi_display_enable(struct omap_dss_device *dssdev)
diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c
index e2f2d6b2aa76..b3bda2d3c08d 100644
--- a/drivers/gpu/drm/omapdrm/dss/sdi.c
+++ b/drivers/gpu/drm/omapdrm/dss/sdi.c
@@ -39,7 +39,7 @@ static struct {
39 struct regulator *vdds_sdi_reg; 39 struct regulator *vdds_sdi_reg;
40 40
41 struct dss_lcd_mgr_config mgr_config; 41 struct dss_lcd_mgr_config mgr_config;
42 struct videomode timings; 42 struct videomode vm;
43 int datapairs; 43 int datapairs;
44 44
45 struct omap_dss_device output; 45 struct omap_dss_device output;
@@ -131,7 +131,7 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
131{ 131{
132 struct omap_dss_device *out = &sdi.output; 132 struct omap_dss_device *out = &sdi.output;
133 enum omap_channel channel = dssdev->dispc_channel; 133 enum omap_channel channel = dssdev->dispc_channel;
134 struct videomode *t = &sdi.timings; 134 struct videomode *vm = &sdi.vm;
135 unsigned long fck; 135 unsigned long fck;
136 struct dispc_clock_info dispc_cinfo; 136 struct dispc_clock_info dispc_cinfo;
137 unsigned long pck; 137 unsigned long pck;
@@ -151,9 +151,9 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
151 goto err_get_dispc; 151 goto err_get_dispc;
152 152
153 /* 15.5.9.1.2 */ 153 /* 15.5.9.1.2 */
154 t->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; 154 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
155 155
156 r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo); 156 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo);
157 if (r) 157 if (r)
158 goto err_calc_clock_div; 158 goto err_calc_clock_div;
159 159
@@ -161,15 +161,15 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
161 161
162 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 162 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
163 163
164 if (pck != t->pixelclock) { 164 if (pck != vm->pixelclock) {
165 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n", 165 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
166 t->pixelclock, pck); 166 vm->pixelclock, pck);
167 167
168 t->pixelclock = pck; 168 vm->pixelclock = pck;
169 } 169 }
170 170
171 171
172 dss_mgr_set_timings(channel, t); 172 dss_mgr_set_timings(channel, vm);
173 173
174 r = dss_set_fck_rate(fck); 174 r = dss_set_fck_rate(fck);
175 if (r) 175 if (r)
@@ -228,26 +228,26 @@ static void sdi_display_disable(struct omap_dss_device *dssdev)
228} 228}
229 229
230static void sdi_set_timings(struct omap_dss_device *dssdev, 230static void sdi_set_timings(struct omap_dss_device *dssdev,
231 struct videomode *timings) 231 struct videomode *vm)
232{ 232{
233 sdi.timings = *timings; 233 sdi.vm = *vm;
234} 234}
235 235
236static void sdi_get_timings(struct omap_dss_device *dssdev, 236static void sdi_get_timings(struct omap_dss_device *dssdev,
237 struct videomode *timings) 237 struct videomode *vm)
238{ 238{
239 *timings = sdi.timings; 239 *vm = sdi.vm;
240} 240}
241 241
242static int sdi_check_timings(struct omap_dss_device *dssdev, 242static int sdi_check_timings(struct omap_dss_device *dssdev,
243 struct videomode *timings) 243 struct videomode *vm)
244{ 244{
245 enum omap_channel channel = dssdev->dispc_channel; 245 enum omap_channel channel = dssdev->dispc_channel;
246 246
247 if (!dispc_mgr_timings_ok(channel, timings)) 247 if (!dispc_mgr_timings_ok(channel, vm))
248 return -EINVAL; 248 return -EINVAL;
249 249
250 if (timings->pixelclock == 0) 250 if (vm->pixelclock == 0)
251 return -EINVAL; 251 return -EINVAL;
252 252
253 return 0; 253 return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c
index 68a04a8753b0..d74f7fcc2e46 100644
--- a/drivers/gpu/drm/omapdrm/dss/venc.c
+++ b/drivers/gpu/drm/omapdrm/dss/venc.c
@@ -262,7 +262,7 @@ static const struct venc_config venc_config_pal_bdghi = {
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005, 262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263}; 263};
264 264
265const struct videomode omap_dss_pal_timings = { 265const struct videomode omap_dss_pal_vm = {
266 .hactive = 720, 266 .hactive = 720,
267 .vactive = 574, 267 .vactive = 574,
268 .pixelclock = 13500000, 268 .pixelclock = 13500000,
@@ -278,9 +278,9 @@ const struct videomode omap_dss_pal_timings = {
278 DISPLAY_FLAGS_PIXDATA_POSEDGE | 278 DISPLAY_FLAGS_PIXDATA_POSEDGE |
279 DISPLAY_FLAGS_SYNC_NEGEDGE, 279 DISPLAY_FLAGS_SYNC_NEGEDGE,
280}; 280};
281EXPORT_SYMBOL(omap_dss_pal_timings); 281EXPORT_SYMBOL(omap_dss_pal_vm);
282 282
283const struct videomode omap_dss_ntsc_timings = { 283const struct videomode omap_dss_ntsc_vm = {
284 .hactive = 720, 284 .hactive = 720,
285 .vactive = 482, 285 .vactive = 482,
286 .pixelclock = 13500000, 286 .pixelclock = 13500000,
@@ -296,7 +296,7 @@ const struct videomode omap_dss_ntsc_timings = {
296 DISPLAY_FLAGS_PIXDATA_POSEDGE | 296 DISPLAY_FLAGS_PIXDATA_POSEDGE |
297 DISPLAY_FLAGS_SYNC_NEGEDGE, 297 DISPLAY_FLAGS_SYNC_NEGEDGE,
298}; 298};
299EXPORT_SYMBOL(omap_dss_ntsc_timings); 299EXPORT_SYMBOL(omap_dss_ntsc_vm);
300 300
301static struct { 301static struct {
302 struct platform_device *pdev; 302 struct platform_device *pdev;
@@ -307,7 +307,7 @@ static struct {
307 307
308 struct clk *tv_dac_clk; 308 struct clk *tv_dac_clk;
309 309
310 struct videomode timings; 310 struct videomode vm;
311 enum omap_dss_venc_type type; 311 enum omap_dss_venc_type type;
312 bool invert_polarity; 312 bool invert_polarity;
313 313
@@ -421,13 +421,12 @@ static void venc_runtime_put(void)
421 WARN_ON(r < 0 && r != -ENOSYS); 421 WARN_ON(r < 0 && r != -ENOSYS);
422} 422}
423 423
424static const struct venc_config *venc_timings_to_config( 424static const struct venc_config *venc_timings_to_config(struct videomode *vm)
425 struct videomode *timings)
426{ 425{
427 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 426 if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
428 return &venc_config_pal_trm; 427 return &venc_config_pal_trm;
429 428
430 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 429 if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
431 return &venc_config_ntsc_trm; 430 return &venc_config_ntsc_trm;
432 431
433 BUG(); 432 BUG();
@@ -445,7 +444,7 @@ static int venc_power_on(struct omap_dss_device *dssdev)
445 goto err0; 444 goto err0;
446 445
447 venc_reset(); 446 venc_reset();
448 venc_write_config(venc_timings_to_config(&venc.timings)); 447 venc_write_config(venc_timings_to_config(&venc.vm));
449 448
450 dss_set_venc_output(venc.type); 449 dss_set_venc_output(venc.type);
451 dss_set_dac_pwrdn_bgz(1); 450 dss_set_dac_pwrdn_bgz(1);
@@ -462,7 +461,7 @@ static int venc_power_on(struct omap_dss_device *dssdev)
462 461
463 venc_write_reg(VENC_OUTPUT_CONTROL, l); 462 venc_write_reg(VENC_OUTPUT_CONTROL, l);
464 463
465 dss_mgr_set_timings(channel, &venc.timings); 464 dss_mgr_set_timings(channel, &venc.vm);
466 465
467 r = regulator_enable(venc.vdda_dac_reg); 466 r = regulator_enable(venc.vdda_dac_reg);
468 if (r) 467 if (r)
@@ -540,17 +539,17 @@ static void venc_display_disable(struct omap_dss_device *dssdev)
540} 539}
541 540
542static void venc_set_timings(struct omap_dss_device *dssdev, 541static void venc_set_timings(struct omap_dss_device *dssdev,
543 struct videomode *timings) 542 struct videomode *vm)
544{ 543{
545 DSSDBG("venc_set_timings\n"); 544 DSSDBG("venc_set_timings\n");
546 545
547 mutex_lock(&venc.venc_lock); 546 mutex_lock(&venc.venc_lock);
548 547
549 /* Reset WSS data when the TV standard changes. */ 548 /* Reset WSS data when the TV standard changes. */
550 if (memcmp(&venc.timings, timings, sizeof(*timings))) 549 if (memcmp(&venc.vm, vm, sizeof(*vm)))
551 venc.wss_data = 0; 550 venc.wss_data = 0;
552 551
553 venc.timings = *timings; 552 venc.vm = *vm;
554 553
555 dispc_set_tv_pclk(13500000); 554 dispc_set_tv_pclk(13500000);
556 555
@@ -558,25 +557,25 @@ static void venc_set_timings(struct omap_dss_device *dssdev,
558} 557}
559 558
560static int venc_check_timings(struct omap_dss_device *dssdev, 559static int venc_check_timings(struct omap_dss_device *dssdev,
561 struct videomode *timings) 560 struct videomode *vm)
562{ 561{
563 DSSDBG("venc_check_timings\n"); 562 DSSDBG("venc_check_timings\n");
564 563
565 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 564 if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
566 return 0; 565 return 0;
567 566
568 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 567 if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
569 return 0; 568 return 0;
570 569
571 return -EINVAL; 570 return -EINVAL;
572} 571}
573 572
574static void venc_get_timings(struct omap_dss_device *dssdev, 573static void venc_get_timings(struct omap_dss_device *dssdev,
575 struct videomode *timings) 574 struct videomode *vm)
576{ 575{
577 mutex_lock(&venc.venc_lock); 576 mutex_lock(&venc.venc_lock);
578 577
579 *timings = venc.timings; 578 *vm = venc.vm;
580 579
581 mutex_unlock(&venc.venc_lock); 580 mutex_unlock(&venc.venc_lock);
582} 581}
@@ -596,7 +595,7 @@ static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
596 595
597 mutex_lock(&venc.venc_lock); 596 mutex_lock(&venc.venc_lock);
598 597
599 config = venc_timings_to_config(&venc.timings); 598 config = venc_timings_to_config(&venc.vm);
600 599
601 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 600 /* Invert due to VENC_L21_WC_CTL:INV=1 */
602 venc.wss_data = (wss ^ 0xfffff) << 8; 601 venc.wss_data = (wss ^ 0xfffff) << 8;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 01:50:14 -0400