diff options
author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-09-22 07:06:50 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-11-02 04:48:18 -0400 |
commit | a85f4a80784b34362568a0ff1f34aaa3357462a0 (patch) | |
tree | e367feb3b39144565afd166341202fd7811395d2 /drivers/gpu/drm/omapdrm/dss | |
parent | 0a30e150f053e609f7820d81efebde28802035f3 (diff) |
drm/omap: omap_display_timings: rename hbp to hback_porch
In preparation to move the stack to use the generic videmode struct for
display timing information rename the hbp member to hback_porch.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss')
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dispc.c | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/display.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dsi.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/rfbi.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/venc.c | 4 |
8 files changed, 27 insertions, 25 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 3f5c57fbfa94..0d115aa6c86e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c | |||
@@ -2190,14 +2190,14 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, | |||
2190 | int i; | 2190 | int i; |
2191 | 2191 | ||
2192 | nonactive = t->hactive + t->hfront_porch + t->hsync_len + | 2192 | nonactive = t->hactive + t->hfront_porch + t->hsync_len + |
2193 | t->hbp - out_width; | 2193 | t->hback_porch - out_width; |
2194 | 2194 | ||
2195 | i = 0; | 2195 | i = 0; |
2196 | if (out_height < height) | 2196 | if (out_height < height) |
2197 | i++; | 2197 | i++; |
2198 | if (out_width < width) | 2198 | if (out_width < width) |
2199 | i++; | 2199 | i++; |
2200 | blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfront_porch) * | 2200 | blank = div_u64((u64)(t->hback_porch + t->hsync_len + t->hfront_porch) * |
2201 | lclk, pclk); | 2201 | lclk, pclk); |
2202 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); | 2202 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); |
2203 | if (blank <= limits[i]) | 2203 | if (blank <= limits[i]) |
@@ -3132,7 +3132,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, | |||
3132 | return false; | 3132 | return false; |
3133 | 3133 | ||
3134 | if (!_dispc_lcd_timings_ok(timings->hsync_len, | 3134 | if (!_dispc_lcd_timings_ok(timings->hsync_len, |
3135 | timings->hfront_porch, timings->hbp, | 3135 | timings->hfront_porch, timings->hback_porch, |
3136 | timings->vsw, timings->vfp, timings->vbp)) | 3136 | timings->vsw, timings->vfp, timings->vbp)) |
3137 | return false; | 3137 | return false; |
3138 | } | 3138 | } |
@@ -3270,11 +3270,11 @@ void dispc_mgr_set_timings(enum omap_channel channel, | |||
3270 | 3270 | ||
3271 | if (dss_mgr_is_lcd(channel)) { | 3271 | if (dss_mgr_is_lcd(channel)) { |
3272 | _dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch, | 3272 | _dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfront_porch, |
3273 | t.hbp, t.vsw, t.vfp, t.vbp, t.vsync_level, | 3273 | t.hback_porch, t.vsw, t.vfp, t.vbp, |
3274 | t.hsync_level, t.data_pclk_edge, t.de_level, | 3274 | t.vsync_level, t.hsync_level, t.data_pclk_edge, |
3275 | t.sync_pclk_edge); | 3275 | t.de_level, t.sync_pclk_edge); |
3276 | 3276 | ||
3277 | xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hbp; | 3277 | xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; |
3278 | ytot = t.vactive + t.vfp + t.vsw + t.vbp; | 3278 | ytot = t.vactive + t.vfp + t.vsw + t.vbp; |
3279 | 3279 | ||
3280 | ht = timings->pixelclock / xtot; | 3280 | ht = timings->pixelclock / xtot; |
@@ -3282,7 +3282,8 @@ void dispc_mgr_set_timings(enum omap_channel channel, | |||
3282 | 3282 | ||
3283 | DSSDBG("pck %u\n", timings->pixelclock); | 3283 | DSSDBG("pck %u\n", timings->pixelclock); |
3284 | DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", | 3284 | DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", |
3285 | t.hsync_len, t.hfront_porch, t.hbp, t.vsw, t.vfp, t.vbp); | 3285 | t.hsync_len, t.hfront_porch, t.hback_porch, |
3286 | t.vsw, t.vfp, t.vbp); | ||
3286 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", | 3287 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
3287 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | 3288 | t.vsync_level, t.hsync_level, t.data_pclk_edge, |
3288 | t.de_level, t.sync_pclk_edge); | 3289 | t.de_level, t.sync_pclk_edge); |
@@ -4225,7 +4226,7 @@ static const struct dispc_errata_i734_data { | |||
4225 | .timings = { | 4226 | .timings = { |
4226 | .hactive = 8, .vactive = 1, | 4227 | .hactive = 8, .vactive = 1, |
4227 | .pixelclock = 16000000, | 4228 | .pixelclock = 16000000, |
4228 | .hsync_len = 8, .hfront_porch = 4, .hbp = 4, | 4229 | .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, |
4229 | .vsw = 1, .vfp = 1, .vbp = 1, | 4230 | .vsw = 1, .vfp = 1, .vbp = 1, |
4230 | .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, | 4231 | .vsync_level = OMAPDSS_SIG_ACTIVE_LOW, |
4231 | .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, | 4232 | .hsync_level = OMAPDSS_SIG_ACTIVE_LOW, |
diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c index f147c6c663d3..336521cdf824 100644 --- a/drivers/gpu/drm/omapdrm/dss/display.c +++ b/drivers/gpu/drm/omapdrm/dss/display.c | |||
@@ -225,7 +225,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm, | |||
225 | 225 | ||
226 | ovt->pixelclock = vm->pixelclock; | 226 | ovt->pixelclock = vm->pixelclock; |
227 | ovt->hactive = vm->hactive; | 227 | ovt->hactive = vm->hactive; |
228 | ovt->hbp = vm->hback_porch; | 228 | ovt->hback_porch = vm->hback_porch; |
229 | ovt->hfront_porch = vm->hfront_porch; | 229 | ovt->hfront_porch = vm->hfront_porch; |
230 | ovt->hsync_len = vm->hsync_len; | 230 | ovt->hsync_len = vm->hsync_len; |
231 | ovt->vactive = vm->vactive; | 231 | ovt->vactive = vm->vactive; |
@@ -258,7 +258,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, | |||
258 | vm->pixelclock = ovt->pixelclock; | 258 | vm->pixelclock = ovt->pixelclock; |
259 | 259 | ||
260 | vm->hactive = ovt->hactive; | 260 | vm->hactive = ovt->hactive; |
261 | vm->hback_porch = ovt->hbp; | 261 | vm->hback_porch = ovt->hback_porch; |
262 | vm->hfront_porch = ovt->hfront_porch; | 262 | vm->hfront_porch = ovt->hfront_porch; |
263 | vm->hsync_len = ovt->hsync_len; | 263 | vm->hsync_len = ovt->hsync_len; |
264 | vm->vactive = ovt->vactive; | 264 | vm->vactive = ovt->vactive; |
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 17eb16f86adc..a542d44ed53a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c | |||
@@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |||
4423 | t->pixelclock = pck; | 4423 | t->pixelclock = pck; |
4424 | t->hactive = ctx->config->timings->hactive; | 4424 | t->hactive = ctx->config->timings->hactive; |
4425 | t->vactive = ctx->config->timings->vactive; | 4425 | t->vactive = ctx->config->timings->vactive; |
4426 | t->hsync_len = t->hfront_porch = t->hbp = t->vsw = 1; | 4426 | t->hsync_len = t->hfront_porch = t->hback_porch = t->vsw = 1; |
4427 | t->vfp = t->vbp = 0; | 4427 | t->vfp = t->vbp = 0; |
4428 | 4428 | ||
4429 | return true; | 4429 | return true; |
@@ -4527,7 +4527,8 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) | |||
4527 | 4527 | ||
4528 | xres = req_vm->hactive; | 4528 | xres = req_vm->hactive; |
4529 | 4529 | ||
4530 | panel_hbl = req_vm->hfront_porch + req_vm->hbp + req_vm->hsync_len; | 4530 | panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + |
4531 | req_vm->hsync_len; | ||
4531 | panel_htot = xres + panel_hbl; | 4532 | panel_htot = xres + panel_hbl; |
4532 | 4533 | ||
4533 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); | 4534 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); |
@@ -4603,7 +4604,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) | |||
4603 | hsa = max(hsa - hse, 1); | 4604 | hsa = max(hsa - hse, 1); |
4604 | } | 4605 | } |
4605 | 4606 | ||
4606 | hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); | 4607 | hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); |
4607 | hbp = max(hbp, 1); | 4608 | hbp = max(hbp, 1); |
4608 | 4609 | ||
4609 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | 4610 | hfp = dsi_hbl - (hss + hsa + hse + hbp); |
@@ -4662,7 +4663,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) | |||
4662 | hsa = 1; | 4663 | hsa = 1; |
4663 | } | 4664 | } |
4664 | 4665 | ||
4665 | hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); | 4666 | hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); |
4666 | hbp = max(hbp, 1); | 4667 | hbp = max(hbp, 1); |
4667 | 4668 | ||
4668 | hfp = dispc_hbl - hsa - hbp; | 4669 | hfp = dispc_hbl - hsa - hbp; |
@@ -4687,7 +4688,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) | |||
4687 | 4688 | ||
4688 | dispc_vm->hfront_porch = hfp; | 4689 | dispc_vm->hfront_porch = hfp; |
4689 | dispc_vm->hsync_len = hsa; | 4690 | dispc_vm->hsync_len = hsa; |
4690 | dispc_vm->hbp = hbp; | 4691 | dispc_vm->hback_porch = hbp; |
4691 | 4692 | ||
4692 | return true; | 4693 | return true; |
4693 | } | 4694 | } |
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c index 26012224e7e4..f986b323764b 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | |||
@@ -297,7 +297,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, | |||
297 | /* video core */ | 297 | /* video core */ |
298 | video_cfg->data_enable_pol = 1; /* It is always 1*/ | 298 | video_cfg->data_enable_pol = 1; /* It is always 1*/ |
299 | video_cfg->hblank = cfg->timings.hfront_porch + | 299 | video_cfg->hblank = cfg->timings.hfront_porch + |
300 | cfg->timings.hbp + cfg->timings.hsync_len; | 300 | cfg->timings.hback_porch + cfg->timings.hsync_len; |
301 | video_cfg->vblank_osc = 0; | 301 | video_cfg->vblank_osc = 0; |
302 | video_cfg->vblank = cfg->timings.vsw + | 302 | video_cfg->vblank = cfg->timings.vsw + |
303 | cfg->timings.vfp + cfg->timings.vbp; | 303 | cfg->timings.vfp + cfg->timings.vbp; |
@@ -320,7 +320,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, | |||
320 | video_cfg->hblank *= 2; | 320 | video_cfg->hblank *= 2; |
321 | video_cfg->v_fc_config.timings.hfront_porch *= 2; | 321 | video_cfg->v_fc_config.timings.hfront_porch *= 2; |
322 | video_cfg->v_fc_config.timings.hsync_len *= 2; | 322 | video_cfg->v_fc_config.timings.hsync_len *= 2; |
323 | video_cfg->v_fc_config.timings.hbp *= 2; | 323 | video_cfg->v_fc_config.timings.hback_porch *= 2; |
324 | } | 324 | } |
325 | } | 325 | } |
326 | 326 | ||
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index 7b7efb6dc5d7..e4a431cb33a4 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | |||
@@ -181,7 +181,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, | |||
181 | omapdss_get_version() == OMAPDSS_VER_OMAP4) | 181 | omapdss_get_version() == OMAPDSS_VER_OMAP4) |
182 | hsync_len_offset = 0; | 182 | hsync_len_offset = 0; |
183 | 183 | ||
184 | timing_h |= FLD_VAL(timings->hbp, 31, 20); | 184 | timing_h |= FLD_VAL(timings->hback_porch, 31, 20); |
185 | timing_h |= FLD_VAL(timings->hfront_porch, 19, 8); | 185 | timing_h |= FLD_VAL(timings->hfront_porch, 19, 8); |
186 | timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0); | 186 | timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0); |
187 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); | 187 | hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); |
@@ -201,7 +201,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | |||
201 | video_fmt->y_res = param->timings.vactive; | 201 | video_fmt->y_res = param->timings.vactive; |
202 | video_fmt->x_res = param->timings.hactive; | 202 | video_fmt->x_res = param->timings.hactive; |
203 | 203 | ||
204 | timings->hbp = param->timings.hbp; | 204 | timings->hback_porch = param->timings.hback_porch; |
205 | timings->hfront_porch = param->timings.hfront_porch; | 205 | timings->hfront_porch = param->timings.hfront_porch; |
206 | timings->hsync_len = param->timings.hsync_len; | 206 | timings->hsync_len = param->timings.hsync_len; |
207 | timings->vbp = param->timings.vbp; | 207 | timings->vbp = param->timings.vbp; |
@@ -224,7 +224,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, | |||
224 | video_fmt->x_res *= 2; | 224 | video_fmt->x_res *= 2; |
225 | timings->hfront_porch *= 2; | 225 | timings->hfront_porch *= 2; |
226 | timings->hsync_len *= 2; | 226 | timings->hsync_len *= 2; |
227 | timings->hbp *= 2; | 227 | timings->hback_porch *= 2; |
228 | } | 228 | } |
229 | } | 229 | } |
230 | 230 | ||
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index b540baf81e0d..f8db4c29be83 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h | |||
@@ -311,7 +311,7 @@ struct omap_video_timings { | |||
311 | /* Unit: pixel clocks */ | 311 | /* Unit: pixel clocks */ |
312 | u16 hfront_porch; /* Horizontal front porch */ | 312 | u16 hfront_porch; /* Horizontal front porch */ |
313 | /* Unit: pixel clocks */ | 313 | /* Unit: pixel clocks */ |
314 | u16 hbp; /* Horizontal back porch */ | 314 | u16 hback_porch; /* Horizontal back porch */ |
315 | /* Unit: line clocks */ | 315 | /* Unit: line clocks */ |
316 | u16 vsw; /* Vertical synchronization pulse width */ | 316 | u16 vsw; /* Vertical synchronization pulse width */ |
317 | /* Unit: line clocks */ | 317 | /* Unit: line clocks */ |
diff --git a/drivers/gpu/drm/omapdrm/dss/rfbi.c b/drivers/gpu/drm/omapdrm/dss/rfbi.c index 32b87bfd6d3f..0f721fbbe570 100644 --- a/drivers/gpu/drm/omapdrm/dss/rfbi.c +++ b/drivers/gpu/drm/omapdrm/dss/rfbi.c | |||
@@ -860,7 +860,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev) | |||
860 | */ | 860 | */ |
861 | rfbi.timings.hsync_len = 1; | 861 | rfbi.timings.hsync_len = 1; |
862 | rfbi.timings.hfront_porch = 1; | 862 | rfbi.timings.hfront_porch = 1; |
863 | rfbi.timings.hbp = 1; | 863 | rfbi.timings.hback_porch = 1; |
864 | rfbi.timings.vsw = 1; | 864 | rfbi.timings.vsw = 1; |
865 | rfbi.timings.vfp = 0; | 865 | rfbi.timings.vfp = 0; |
866 | rfbi.timings.vbp = 0; | 866 | rfbi.timings.vbp = 0; |
diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c index 92dbcab2d72a..f192368bec60 100644 --- a/drivers/gpu/drm/omapdrm/dss/venc.c +++ b/drivers/gpu/drm/omapdrm/dss/venc.c | |||
@@ -268,7 +268,7 @@ const struct omap_video_timings omap_dss_pal_timings = { | |||
268 | .pixelclock = 13500000, | 268 | .pixelclock = 13500000, |
269 | .hsync_len = 64, | 269 | .hsync_len = 64, |
270 | .hfront_porch = 12, | 270 | .hfront_porch = 12, |
271 | .hbp = 68, | 271 | .hback_porch = 68, |
272 | .vsw = 5, | 272 | .vsw = 5, |
273 | .vfp = 5, | 273 | .vfp = 5, |
274 | .vbp = 41, | 274 | .vbp = 41, |
@@ -289,7 +289,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = { | |||
289 | .pixelclock = 13500000, | 289 | .pixelclock = 13500000, |
290 | .hsync_len = 64, | 290 | .hsync_len = 64, |
291 | .hfront_porch = 16, | 291 | .hfront_porch = 16, |
292 | .hbp = 58, | 292 | .hback_porch = 58, |
293 | .vsw = 6, | 293 | .vsw = 6, |
294 | .vfp = 6, | 294 | .vfp = 6, |
295 | .vbp = 31, | 295 | .vbp = 31, |