drm/omap: omap_display_timings: rename hsw to hsync_len

In preparation to move the stack to use the generic videmode struct for
display timing information rename the hsw member to hsync_len.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

8 files changed, 42 insertions, 41 deletions

diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 3d208ce67794..8f97a11a2e97 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -2189,14 +2189,14 @@ static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
         u64 val, blank;
         int i;
 
-        nonactive = t->hactive + t->hfp + t->hsw + t->hbp - out_width;
+        nonactive = t->hactive + t->hfp + t->hsync_len + t->hbp - out_width;
 
         i = 0;
         if (out_height < height)
                 i++;
         if (out_width < width)
                 i++;
-        blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
+        blank = div_u64((u64)(t->hbp + t->hsync_len + t->hfp) * lclk, pclk);
         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
         if (blank <= limits[i])
                 return -EINVAL;
@@ -3093,10 +3093,10 @@ static bool _dispc_mgr_size_ok(u16 width, u16 height)
                 height <= dispc.feat->mgr_height_max;
 }
 
-static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
+static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp,
                 int vsw, int vfp, int vbp)
 {
-        if (hsw < 1 || hsw > dispc.feat->sw_max ||
+        if (hsync_len < 1 || hsync_len > dispc.feat->sw_max ||
                         hfp < 1 || hfp > dispc.feat->hp_max ||
                         hbp < 1 || hbp > dispc.feat->hp_max ||
                         vsw < 1 || vsw > dispc.feat->sw_max ||
@@ -3129,7 +3129,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
                 if (timings->interlace)
                         return false;
 
-                if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
+                if (!_dispc_lcd_timings_ok(timings->hsync_len, timings->hfp,
                                 timings->hbp, timings->vsw, timings->vfp,
                                 timings->vbp))
                         return false;
@@ -3138,7 +3138,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel,
         return true;
 }
 
-static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
+static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsync_len,
                 int hfp, int hbp, int vsw, int vfp, int vbp,
                 enum omap_dss_signal_level vsync_level,
                 enum omap_dss_signal_level hsync_level,
@@ -3150,7 +3150,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
         u32 timing_h, timing_v, l;
         bool onoff, rf, ipc, vs, hs, de;
 
-        timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
+        timing_h = FLD_VAL(hsync_len-1, dispc.feat->sw_start, 0) |
                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
@@ -3267,19 +3267,20 @@ void dispc_mgr_set_timings(enum omap_channel channel,
         }
 
         if (dss_mgr_is_lcd(channel)) {
-                _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
-                                t.vfp, t.vbp, t.vsync_level, t.hsync_level,
-                                t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
+                _dispc_mgr_set_lcd_timings(channel, t.hsync_len, t.hfp, t.hbp,
+                                t.vsw, t.vfp, t.vbp, t.vsync_level,
+                                t.hsync_level, t.data_pclk_edge, t.de_level,
+                                t.sync_pclk_edge);
 
-                xtot = t.hactive + t.hfp + t.hsw + t.hbp;
+                xtot = t.hactive + t.hfp + t.hsync_len + t.hbp;
                 ytot = t.vactive + t.vfp + t.vsw + t.vbp;
 
                 ht = timings->pixelclock / xtot;
                 vt = timings->pixelclock / xtot / ytot;
 
                 DSSDBG("pck %u\n", timings->pixelclock);
-                DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
-                        t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
+                DSSDBG("hsync_len %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
+                        t.hsync_len, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
                         t.de_level, t.sync_pclk_edge);
@@ -4222,7 +4223,7 @@ static const struct dispc_errata_i734_data {
         .timings = {
                 .hactive = 8, .vactive = 1,
                 .pixelclock = 16000000,
-                .hsw = 8, .hfp = 4, .hbp = 4,
+                .hsync_len = 8, .hfp = 4, .hbp = 4,
                 .vsw = 1, .vfp = 1, .vbp = 1,
                 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
                 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c
index 29ae5d6e1508..78ceaa5e8198 100644
--- a/drivers/gpu/drm/omapdrm/dss/display.c
+++ b/drivers/gpu/drm/omapdrm/dss/display.c
@@ -227,7 +227,7 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
         ovt->hactive = vm->hactive;
         ovt->hbp = vm->hback_porch;
         ovt->hfp = vm->hfront_porch;
-        ovt->hsw = vm->hsync_len;
+        ovt->hsync_len = vm->hsync_len;
         ovt->vactive = vm->vactive;
         ovt->vbp = vm->vback_porch;
         ovt->vfp = vm->vfront_porch;
@@ -260,7 +260,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
         vm->hactive = ovt->hactive;
         vm->hback_porch = ovt->hbp;
         vm->hfront_porch = ovt->hfp;
-        vm->hsync_len = ovt->hsw;
+        vm->hsync_len = ovt->hsync_len;
         vm->vactive = ovt->vactive;
         vm->vback_porch = ovt->vbp;
         vm->vfront_porch = ovt->vfp;
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 06b15091d62f..002b450b0649 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -4362,7 +4362,7 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
         int hact, bl, tot;
 
         hact = t->hactive;
-        bl = t->hsw + t->hbp + t->hfp;
+        bl = t->hsync_len + t->hbp + t->hfp;
         tot = hact + bl;
 
 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
@@ -4371,9 +4371,9 @@ static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
                         "%u/%u/%u/%u = %u + %u = %u\n",
                         str,
                         pck,
-                        t->hsw, t->hbp, hact, t->hfp,
+                        t->hsync_len, t->hbp, hact, t->hfp,
                         bl, hact, tot,
-                        TO_DISPC_T(t->hsw),
+                        TO_DISPC_T(t->hsync_len),
                         TO_DISPC_T(t->hbp),
                         TO_DISPC_T(hact),
                         TO_DISPC_T(t->hfp),
@@ -4399,7 +4399,7 @@ static void print_dsi_dispc_vm(const char *str,
         dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
 
         vm.pixelclock = pck;
-        vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
+        vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
         vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
         vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
         vm.hactive = t->hact;
@@ -4423,7 +4423,7 @@ static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
         t->pixelclock = pck;
         t->hactive = ctx->config->timings->hactive;
         t->vactive = ctx->config->timings->vactive;
-        t->hsw = t->hfp = t->hbp = t->vsw = 1;
+        t->hsync_len = t->hfp = t->hbp = t->vsw = 1;
         t->vfp = t->vbp = 0;
 
         return true;
@@ -4527,7 +4527,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
 
         xres = req_vm->hactive;
 
-        panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
+        panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsync_len;
         panel_htot = xres + panel_hbl;
 
         dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
@@ -4557,7 +4557,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
         hss = DIV_ROUND_UP(4, ndl);
 
         if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
-                if (ndl == 3 && req_vm->hsw == 0)
+                if (ndl == 3 && req_vm->hsync_len == 0)
                         hse = 1;
                 else
                         hse = DIV_ROUND_UP(4, ndl);
@@ -4596,10 +4596,10 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
 
         if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
                 hsa = 0;
-        } else if (ndl == 3 && req_vm->hsw == 0) {
+        } else if (ndl == 3 && req_vm->hsync_len == 0) {
                 hsa = 0;
         } else {
-                hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
+                hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
                 hsa = max(hsa - hse, 1);
         }
 
@@ -4655,7 +4655,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
         dispc_vm->pixelclock = dispc_pck;
 
         if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
-                hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
+                hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
                                 req_pck_nom);
                 hsa = max(hsa, 1);
         } else {
@@ -4686,7 +4686,7 @@ static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
                 return false;
 
         dispc_vm->hfp = hfp;
-        dispc_vm->hsw = hsa;
+        dispc_vm->hsync_len = hsa;
         dispc_vm->hbp = hbp;
 
         return true;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 3f76976b0e38..dd4c989c44ce 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -297,7 +297,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
         /* video core */
         video_cfg->data_enable_pol = 1; /* It is always 1*/
         video_cfg->hblank = cfg->timings.hfp +
-                                cfg->timings.hbp + cfg->timings.hsw;
+                                cfg->timings.hbp + cfg->timings.hsync_len;
         video_cfg->vblank_osc = 0;
         video_cfg->vblank = cfg->timings.vsw +
                                 cfg->timings.vfp + cfg->timings.vbp;
@@ -319,7 +319,7 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
                 video_cfg->v_fc_config.timings.hactive *= 2;
                 video_cfg->hblank *= 2;
                 video_cfg->v_fc_config.timings.hfp *= 2;
-                video_cfg->v_fc_config.timings.hsw *= 2;
+                video_cfg->v_fc_config.timings.hsync_len *= 2;
                 video_cfg->v_fc_config.timings.hbp *= 2;
         }
 }
@@ -377,9 +377,9 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
 
         /* set horizontal sync pulse width */
         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
-                        (cfg->v_fc_config.timings.hsw >> 8), 1, 0);
+                        (cfg->v_fc_config.timings.hsync_len >> 8), 1, 0);
         REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
-                        cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
+                        cfg->v_fc_config.timings.hsync_len & 0xFF, 7, 0);
 
         /*  set vertical sync pulse width */
         REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index 05462cfe5af8..89914a7a2bf9 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -166,24 +166,24 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 {
         u32 timing_h = 0;
         u32 timing_v = 0;
-        unsigned hsw_offset = 1;
+        unsigned hsync_len_offset = 1;
 
         DSSDBG("Enter hdmi_wp_video_config_timing\n");
 
         /*
          * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
-         * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1.
+         * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.
          * However, we don't support OMAP5 ES1 at all, so we can just check for
          * OMAP4 here.
          */
         if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
             omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
             omapdss_get_version() == OMAPDSS_VER_OMAP4)
-                hsw_offset = 0;
+                hsync_len_offset = 0;
 
         timing_h |= FLD_VAL(timings->hbp, 31, 20);
         timing_h |= FLD_VAL(timings->hfp, 19, 8);
-        timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0);
+        timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0);
         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
 
         timing_v |= FLD_VAL(timings->vbp, 31, 20);
@@ -203,7 +203,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 
         timings->hbp = param->timings.hbp;
         timings->hfp = param->timings.hfp;
-        timings->hsw = param->timings.hsw;
+        timings->hsync_len = param->timings.hsync_len;
         timings->vbp = param->timings.vbp;
         timings->vfp = param->timings.vfp;
         timings->vsw = param->timings.vsw;
@@ -223,7 +223,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
         if (param->timings.double_pixel) {
                 video_fmt->x_res *= 2;
                 timings->hfp *= 2;
-                timings->hsw *= 2;
+                timings->hsync_len *= 2;
                 timings->hbp *= 2;
         }
 }
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index 0b969f6f5701..6468afa2a85b 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -307,7 +307,7 @@ struct omap_video_timings {
         /* Unit: Hz */
         u32 pixelclock;
         /* Unit: pixel clocks */
-        u16 hsw;        /* Horizontal synchronization pulse width */
+        u16 hsync_len;          /* Horizontal synchronization pulse width */
         /* Unit: pixel clocks */
         u16 hfp;        /* Horizontal front porch */
         /* Unit: pixel clocks */
diff --git a/drivers/gpu/drm/omapdrm/dss/rfbi.c b/drivers/gpu/drm/omapdrm/dss/rfbi.c
index ef9984c3d906..11d70691c4b1 100644
--- a/drivers/gpu/drm/omapdrm/dss/rfbi.c
+++ b/drivers/gpu/drm/omapdrm/dss/rfbi.c
@@ -858,7 +858,7 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
          * are expected to be already configured by the panel driver via
          * omapdss_rfbi_set_size()
          */
-        rfbi.timings.hsw = 1;
+        rfbi.timings.hsync_len = 1;
         rfbi.timings.hfp = 1;
         rfbi.timings.hbp = 1;
         rfbi.timings.vsw = 1;
diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c
index 463dc4e27f7a..9f53e9a21706 100644
--- a/drivers/gpu/drm/omapdrm/dss/venc.c
+++ b/drivers/gpu/drm/omapdrm/dss/venc.c
@@ -266,7 +266,7 @@ const struct omap_video_timings omap_dss_pal_timings = {
         .hactive        = 720,
         .vactive        = 574,
         .pixelclock     = 13500000,
-        .hsw            = 64,
+        .hsync_len      = 64,
         .hfp            = 12,
         .hbp            = 68,
         .vsw            = 5,
@@ -287,7 +287,7 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
         .hactive        = 720,
         .vactive        = 482,
         .pixelclock     = 13500000,
-        .hsw            = 64,
+        .hsync_len      = 64,
         .hfp            = 16,
         .hbp            = 58,
         .vsw            = 6,