diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-22 01:03:09 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:12:56 -0400 |
commit | 08c770969a45361277d556f9fd3e2d70da42be65 (patch) | |
tree | b4bfae82cf944404e60bfe7a5d36cf8796433bb5 /drivers/gpu/drm/nouveau/nouveau_drv.h | |
parent | ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69 (diff) |
drm/nouveau: start culling unused code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.h')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 135 |
1 files changed, 0 insertions, 135 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index f1cce652a2a9..16b7bb6951cc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -64,15 +64,10 @@ enum blah { | |||
64 | NV_MEM_TYPE_GDDR5 | 64 | NV_MEM_TYPE_GDDR5 |
65 | }; | 65 | }; |
66 | 66 | ||
67 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | ||
68 | |||
69 | #include <nouveau_drm.h> | 67 | #include <nouveau_drm.h> |
70 | #include "nouveau_reg.h" | 68 | #include "nouveau_reg.h" |
71 | #include <nouveau_bios.h> | 69 | #include <nouveau_bios.h> |
72 | 70 | ||
73 | struct nouveau_grctx; | ||
74 | struct nouveau_mem; | ||
75 | |||
76 | #include <subdev/bios/pll.h> | 71 | #include <subdev/bios/pll.h> |
77 | #include "nouveau_compat.h" | 72 | #include "nouveau_compat.h" |
78 | 73 | ||
@@ -85,18 +80,9 @@ struct nouveau_mem; | |||
85 | #define nv50_vm_flush_engine(d,e) \ | 80 | #define nv50_vm_flush_engine(d,e) \ |
86 | _nv50_vm_flush_engine((d), (e)) | 81 | _nv50_vm_flush_engine((d), (e)) |
87 | 82 | ||
88 | #define MAX_NUM_DCB_ENTRIES 16 | ||
89 | |||
90 | #define NOUVEAU_MAX_CHANNEL_NR 4096 | ||
91 | |||
92 | #include "nouveau_bo.h" | 83 | #include "nouveau_bo.h" |
93 | #include "nouveau_gem.h" | 84 | #include "nouveau_gem.h" |
94 | 85 | ||
95 | enum nouveau_flags { | ||
96 | NV_NFORCE = 0x10000000, | ||
97 | NV_NFORCE2 = 0x20000000 | ||
98 | }; | ||
99 | |||
100 | struct nouveau_page_flip_state { | 86 | struct nouveau_page_flip_state { |
101 | struct list_head head; | 87 | struct list_head head; |
102 | struct drm_pending_vblank_event *event; | 88 | struct drm_pending_vblank_event *event; |
@@ -104,11 +90,6 @@ struct nouveau_page_flip_state { | |||
104 | uint64_t offset; | 90 | uint64_t offset; |
105 | }; | 91 | }; |
106 | 92 | ||
107 | enum nouveau_channel_mutex_class { | ||
108 | NOUVEAU_UCHANNEL_MUTEX, | ||
109 | NOUVEAU_KCHANNEL_MUTEX | ||
110 | }; | ||
111 | |||
112 | struct nouveau_display_engine { | 93 | struct nouveau_display_engine { |
113 | void *priv; | 94 | void *priv; |
114 | int (*early_init)(struct drm_device *); | 95 | int (*early_init)(struct drm_device *); |
@@ -306,11 +287,8 @@ enum nouveau_card_type { | |||
306 | NV_E0 = 0xe0, | 287 | NV_E0 = 0xe0, |
307 | }; | 288 | }; |
308 | 289 | ||
309 | struct nouveau_channel; | ||
310 | |||
311 | struct drm_nouveau_private { | 290 | struct drm_nouveau_private { |
312 | struct drm_device *dev; | 291 | struct drm_device *dev; |
313 | bool noaccel; | ||
314 | 292 | ||
315 | void *newpriv; | 293 | void *newpriv; |
316 | 294 | ||
@@ -318,11 +296,8 @@ struct drm_nouveau_private { | |||
318 | enum nouveau_card_type card_type; | 296 | enum nouveau_card_type card_type; |
319 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | 297 | /* exact chipset, derived from NV_PMC_BOOT_0 */ |
320 | int chipset; | 298 | int chipset; |
321 | int flags; | ||
322 | u32 crystal; | 299 | u32 crystal; |
323 | 300 | ||
324 | struct nouveau_bo *vga_ram; | ||
325 | |||
326 | /* interrupt handling */ | 301 | /* interrupt handling */ |
327 | void (*irq_handler[32])(struct drm_device *); | 302 | void (*irq_handler[32])(struct drm_device *); |
328 | bool msi_enabled; | 303 | bool msi_enabled; |
@@ -332,16 +307,8 @@ struct drm_nouveau_private { | |||
332 | /* For PFIFO and PGRAPH. */ | 307 | /* For PFIFO and PGRAPH. */ |
333 | spinlock_t context_switch_lock; | 308 | spinlock_t context_switch_lock; |
334 | 309 | ||
335 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ | ||
336 | struct nouveau_ramht *ramht; | ||
337 | |||
338 | uint64_t fb_available_size; | ||
339 | uint64_t fb_mappable_pages; | ||
340 | int fb_mtrr; | ||
341 | |||
342 | struct nvbios vbios; | 310 | struct nvbios vbios; |
343 | u8 *mxms; | 311 | u8 *mxms; |
344 | struct list_head i2c_ports; | ||
345 | 312 | ||
346 | struct backlight_device *backlight; | 313 | struct backlight_device *backlight; |
347 | }; | 314 | }; |
@@ -363,9 +330,7 @@ extern char *nouveau_vram_type; | |||
363 | extern int nouveau_fbpercrtc; | 330 | extern int nouveau_fbpercrtc; |
364 | extern int nouveau_tv_disable; | 331 | extern int nouveau_tv_disable; |
365 | extern char *nouveau_tv_norm; | 332 | extern char *nouveau_tv_norm; |
366 | extern int nouveau_reg_debug; | ||
367 | extern int nouveau_ignorelid; | 333 | extern int nouveau_ignorelid; |
368 | extern int nouveau_noaccel; | ||
369 | extern int nouveau_force_post; | 334 | extern int nouveau_force_post; |
370 | extern int nouveau_override_conntype; | 335 | extern int nouveau_override_conntype; |
371 | extern char *nouveau_perflvl; | 336 | extern char *nouveau_perflvl; |
@@ -382,34 +347,13 @@ extern int nouveau_load(struct drm_device *, unsigned long flags); | |||
382 | extern int nouveau_firstopen(struct drm_device *); | 347 | extern int nouveau_firstopen(struct drm_device *); |
383 | extern void nouveau_lastclose(struct drm_device *); | 348 | extern void nouveau_lastclose(struct drm_device *); |
384 | extern int nouveau_unload(struct drm_device *); | 349 | extern int nouveau_unload(struct drm_device *); |
385 | extern bool nouveau_wait_for_idle(struct drm_device *); | ||
386 | extern int nouveau_card_init(struct drm_device *); | 350 | extern int nouveau_card_init(struct drm_device *); |
387 | 351 | ||
388 | /* nouveau_mem.c */ | 352 | /* nouveau_mem.c */ |
389 | extern int nouveau_mem_vram_init(struct drm_device *); | ||
390 | extern void nouveau_mem_vram_fini(struct drm_device *); | ||
391 | extern int nouveau_mem_gart_init(struct drm_device *); | ||
392 | extern void nouveau_mem_gart_fini(struct drm_device *); | ||
393 | extern void nouveau_mem_close(struct drm_device *); | ||
394 | extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); | ||
395 | extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, | 353 | extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, |
396 | struct nouveau_pm_memtiming *); | 354 | struct nouveau_pm_memtiming *); |
397 | extern void nouveau_mem_timing_read(struct drm_device *, | 355 | extern void nouveau_mem_timing_read(struct drm_device *, |
398 | struct nouveau_pm_memtiming *); | 356 | struct nouveau_pm_memtiming *); |
399 | extern int nouveau_mem_vbios_type(struct drm_device *); | ||
400 | extern struct nouveau_tile_reg *nv10_mem_set_tiling( | ||
401 | struct drm_device *dev, uint32_t addr, uint32_t size, | ||
402 | uint32_t pitch, uint32_t flags); | ||
403 | extern void nv10_mem_put_tile_region(struct drm_device *dev, | ||
404 | struct nouveau_tile_reg *tile, | ||
405 | struct nouveau_fence *fence); | ||
406 | |||
407 | extern int nouveau_channel_idle(struct nouveau_channel *chan); | ||
408 | |||
409 | /* nouveau_gpuobj.c */ | ||
410 | int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm, | ||
411 | u32 flags, struct nouveau_vma *vma); | ||
412 | void nouveau_gpuobj_unmap(struct nouveau_vma *vma); | ||
413 | 357 | ||
414 | /* nouveau_irq.c */ | 358 | /* nouveau_irq.c */ |
415 | extern int nouveau_irq_init(struct drm_device *); | 359 | extern int nouveau_irq_init(struct drm_device *); |
@@ -586,26 +530,6 @@ int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, | |||
586 | } \ | 530 | } \ |
587 | } while(0) | 531 | } while(0) |
588 | 532 | ||
589 | /* nouveau_reg_debug bitmask */ | ||
590 | enum { | ||
591 | NOUVEAU_REG_DEBUG_MC = 0x1, | ||
592 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | ||
593 | NOUVEAU_REG_DEBUG_FB = 0x4, | ||
594 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | ||
595 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | ||
596 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | ||
597 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | ||
598 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | ||
599 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | ||
600 | NOUVEAU_REG_DEBUG_EVO = 0x200, | ||
601 | NOUVEAU_REG_DEBUG_AUXCH = 0x400 | ||
602 | }; | ||
603 | |||
604 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | ||
605 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | ||
606 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | ||
607 | } while (0) | ||
608 | |||
609 | static inline bool | 533 | static inline bool |
610 | nv_two_heads(struct drm_device *dev) | 534 | nv_two_heads(struct drm_device *dev) |
611 | { | 535 | { |
@@ -645,63 +569,4 @@ nv_match_device(struct drm_device *dev, unsigned device, | |||
645 | dev->pdev->subsystem_device == sub_device; | 569 | dev->pdev->subsystem_device == sub_device; |
646 | } | 570 | } |
647 | 571 | ||
648 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, | ||
649 | * helpful to determine a number of other hardware features | ||
650 | */ | ||
651 | static inline int | ||
652 | nv44_graph_class(struct drm_device *dev) | ||
653 | { | ||
654 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
655 | |||
656 | if ((dev_priv->chipset & 0xf0) == 0x60) | ||
657 | return 1; | ||
658 | |||
659 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | ||
660 | } | ||
661 | |||
662 | /* memory type/access flags, do not match hardware values */ | ||
663 | #define NV_MEM_ACCESS_RO 1 | ||
664 | #define NV_MEM_ACCESS_WO 2 | ||
665 | #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) | ||
666 | #define NV_MEM_ACCESS_SYS 4 | ||
667 | #define NV_MEM_ACCESS_VM 8 | ||
668 | #define NV_MEM_ACCESS_NOSNOOP 16 | ||
669 | |||
670 | #define NV_MEM_TARGET_VRAM 0 | ||
671 | #define NV_MEM_TARGET_PCI 1 | ||
672 | #define NV_MEM_TARGET_PCI_NOSNOOP 2 | ||
673 | #define NV_MEM_TARGET_VM 3 | ||
674 | #define NV_MEM_TARGET_GART 4 | ||
675 | |||
676 | #define NV_MEM_TYPE_VM 0x7f | ||
677 | #define NV_MEM_COMP_VM 0x03 | ||
678 | |||
679 | /* FIFO methods */ | ||
680 | #define NV01_SUBCHAN_OBJECT 0x00000000 | ||
681 | #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 | ||
682 | #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 | ||
683 | #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 | ||
684 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c | ||
685 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 | ||
686 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 | ||
687 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 | ||
688 | #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 | ||
689 | #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020 | ||
690 | #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 | ||
691 | #define NV10_SUBCHAN_REF_CNT 0x00000050 | ||
692 | #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054 | ||
693 | #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 | ||
694 | #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 | ||
695 | #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 | ||
696 | #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c | ||
697 | #define NV40_SUBCHAN_YIELD 0x00000080 | ||
698 | |||
699 | /* NV_SW object class */ | ||
700 | #define NV_SW 0x0000506e | ||
701 | #define NV_SW_DMA_VBLSEM 0x0000018c | ||
702 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | ||
703 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | ||
704 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | ||
705 | #define NV_SW_PAGE_FLIP 0x00000500 | ||
706 | |||
707 | #endif /* __NOUVEAU_DRV_H__ */ | 572 | #endif /* __NOUVEAU_DRV_H__ */ |