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authorDave Airlie <airlied@redhat.com>2017-06-19 21:10:49 -0400
committerDave Airlie <airlied@redhat.com>2017-06-19 21:10:49 -0400
commitd02b0ffb005469ef4ee73610fb08dff45e4487f8 (patch)
tree3acf65e7109cbbde522ec0d9fa5cfc6064a8428c /drivers/gpu/drm/nouveau/include/nvkm/subdev
parent4a525bad68b424d167042342db19d0c0e80e8b29 (diff)
parent7df1bb87b8cb0b618e4b5964f89d81d8ce52c58e (diff)
Merge branch 'linux-4.13' of git://github.com/skeggsb/linux into drm-next
- HDMI stereoscopic support - Rework of display code to properly support SOR pad macro routing on >=GM20x GPUs - Various other fixes/improvements. * 'linux-4.13' of git://github.com/skeggsb/linux: (73 commits) drm/nouveau/disp/nv50-: avoid creating ORs that aren't present on HW drm/nouveau: use proper prototype in nouveau_pmops_runtime() definition drm/nouveau: Skip vga_fini on non-PCI device drm/nouveau/tegra: Don't leave GPU in reset drm/nouveau/tegra: Skip manual unpowergating when not necessary drm/nouveau/hwmon: Change permissions to numeric drm/nouveau/hwmon: expose the auto_point and pwm_min/max attrs drm/nouveau/hwmon: Remove old code, add .write/.read operations drm/nouveau/hwmon: Add nouveau_hwmon_ops structure with .is_visible/.read_string drm/nouveau/hwmon: Add config for all sensors and their settings drm/nouveau/disp/gm200-: allow non-identity mapping of SOR <-> macro links drm/nouveau/disp/nv50-: implement a common supervisor 3.0 drm/nouveau/disp/nv50-: implement a common supervisor 2.2 drm/nouveau/disp/nv50-: implement a common supervisor 2.1 drm/nouveau/disp/nv50-: implement a common supervisor 2.0 drm/nouveau/disp/nv50-: implement a common supervisor 1.0 drm/nouveau/disp/nv50-gt21x: remove workaround for dp->tmds hotplug issues drm/nouveau/disp/dp: use new devinit script interpreter entry-point drm/nouveau/disp/dp: determine link bandwidth requirements from head state drm/nouveau/disp: introduce acquire/release display path methods ...
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvkm/subdev')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h27
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h1
2 files changed, 21 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
index 4dc1c8af840c..06ab48052128 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/init.h
@@ -3,19 +3,34 @@
3 3
4struct nvbios_init { 4struct nvbios_init {
5 struct nvkm_subdev *subdev; 5 struct nvkm_subdev *subdev;
6 struct nvkm_bios *bios; 6 u32 offset;
7 u16 offset; 7
8 struct dcb_output *outp; 8 struct dcb_output *outp;
9 int crtc; 9 int or;
10 int link;
11 int head;
10 12
11 /* internal state used during parsing */ 13 /* internal state used during parsing */
12 u8 execute; 14 u8 execute;
13 u32 nested; 15 u32 nested;
14 u16 repeat; 16 u32 repeat;
15 u16 repend; 17 u32 repend;
16 u32 ramcfg; 18 u32 ramcfg;
17}; 19};
18 20
21#define nvbios_init(s,o,ARGS...) ({ \
22 struct nvbios_init init = { \
23 .subdev = (s), \
24 .offset = (o), \
25 .or = -1, \
26 .link = 0, \
27 .head = -1, \
28 .execute = 1, \
29 }; \
30 ARGS \
31 nvbios_exec(&init); \
32})
19int nvbios_exec(struct nvbios_init *); 33int nvbios_exec(struct nvbios_init *);
20int nvbios_init(struct nvkm_subdev *, bool execute); 34
35int nvbios_post(struct nvkm_subdev *, bool execute);
21#endif 36#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
index 820a4805916f..ff0709652f80 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h
@@ -26,7 +26,6 @@ struct nvkm_timer {
26 26
27u64 nvkm_timer_read(struct nvkm_timer *); 27u64 nvkm_timer_read(struct nvkm_timer *);
28void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *); 28void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *);
29void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *);
30 29
31/* Delay based on GPU time (ie. PTIMER). 30/* Delay based on GPU time (ie. PTIMER).
32 * 31 *