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authorStephen Boyd <swboyd@chromium.org>2019-01-03 14:06:02 -0500
committerSean Paul <seanpaul@chromium.org>2019-02-01 10:35:55 -0500
commit070e64dc1bbc879b7e0e9fffccd9dd139baf89f0 (patch)
tree936588e225c1aabc291c540bb443c3fb6bfa44b4 /drivers/gpu/drm/msm
parent7579cb0533d7ce92b52cd40c9080e690e6548b5a (diff)
drm/msm/dpu: Convert to a chained irq chip
Devices that make up DPU, i.e. graphics card, request their interrupts from this "virtual" interrupt chip. The interrupt chip builds upon a GIC SPI interrupt that raises high when any of the interrupts in the DPU's irq status register are triggered. From the kernel's perspective this is a chained irq chip, so requesting a flow handler for the GIC SPI and then calling generic IRQ handling code from that irq handler is not completely proper. It's better to convert this to a chained irq so that the GIC SPI irq doesn't appear in /proc/interrupts, can't have CPU affinity changed, and won't be accounted for with irq stats. Doing this also silences a recursive lockdep warning because we can specify a different lock class for the chained interrupts, silencing a warning that is easy to see with 'threadirqs' on the kernel commandline. WARNING: inconsistent lock state 4.19.10 #76 Tainted: G W -------------------------------- inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. irq/40-dpu_mdss/203 [HC0[0]:SC0[2]:HE1:SE0] takes: 0000000053ea9021 (&irq_desc_lock_class){?.-.}, at: handle_level_irq+0x34/0x26c {IN-HARDIRQ-W} state was registered at: lock_acquire+0x244/0x360 _raw_spin_lock+0x64/0xa0 handle_fasteoi_irq+0x54/0x2ec generic_handle_irq+0x44/0x5c __handle_domain_irq+0x9c/0x11c gic_handle_irq+0x208/0x260 el1_irq+0xb4/0x130 arch_cpu_idle+0x178/0x3cc default_idle_call+0x3c/0x54 do_idle+0x1a8/0x3dc cpu_startup_entry+0x24/0x28 rest_init+0x240/0x270 start_kernel+0x5a8/0x6bc irq event stamp: 18 hardirqs last enabled at (17): [<ffffff9042385e80>] _raw_spin_unlock_irq+0x40/0xc0 hardirqs last disabled at (16): [<ffffff904237a1f4>] __schedule+0x20c/0x1bbc softirqs last enabled at (0): [<ffffff9040f318d0>] copy_process+0xb50/0x3964 softirqs last disabled at (18): [<ffffff9041036364>] local_bh_disable+0x8/0x20 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); <Interrupt> lock(&irq_desc_lock_class); *** DEADLOCK *** no locks held by irq/40-dpu_mdss/203. stack backtrace: CPU: 0 PID: 203 Comm: irq/40-dpu_mdss Tainted: G W 4.19.10 #76 Call trace: dump_backtrace+0x0/0x2f8 show_stack+0x20/0x2c __dump_stack+0x20/0x28 dump_stack+0xcc/0x10c mark_lock+0xbe0/0xe24 __lock_acquire+0x4cc/0x2708 lock_acquire+0x244/0x360 _raw_spin_lock+0x64/0xa0 handle_level_irq+0x34/0x26c generic_handle_irq+0x44/0x5c dpu_mdss_irq+0x64/0xec irq_forced_thread_fn+0x58/0x9c irq_thread+0x120/0x1dc kthread+0x248/0x260 ret_from_fork+0x10/0x18 ------------[ cut here ]------------ irq 169 handler irq_default_primary_handler+0x0/0x18 enabled interrupts Cc: Sean Paul <seanpaul@chromium.org> Cc: Jordan Crouse <jcrouse@codeaurora.org> Cc: Jayant Shekhar <jshekhar@codeaurora.org> Cc: Rajesh Yadav <ryadav@codeaurora.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm')
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c36
1 files changed, 21 insertions, 15 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index cb307a2abf06..7316b4ab1b85 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -23,11 +23,14 @@ struct dpu_mdss {
23 struct dpu_irq_controller irq_controller; 23 struct dpu_irq_controller irq_controller;
24}; 24};
25 25
26static irqreturn_t dpu_mdss_irq(int irq, void *arg) 26static void dpu_mdss_irq(struct irq_desc *desc)
27{ 27{
28 struct dpu_mdss *dpu_mdss = arg; 28 struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc);
29 struct irq_chip *chip = irq_desc_get_chip(desc);
29 u32 interrupts; 30 u32 interrupts;
30 31
32 chained_irq_enter(chip, desc);
33
31 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS); 34 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS);
32 35
33 while (interrupts) { 36 while (interrupts) {
@@ -39,20 +42,20 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg)
39 hwirq); 42 hwirq);
40 if (mapping == 0) { 43 if (mapping == 0) {
41 DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq); 44 DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq);
42 return IRQ_NONE; 45 break;
43 } 46 }
44 47
45 rc = generic_handle_irq(mapping); 48 rc = generic_handle_irq(mapping);
46 if (rc < 0) { 49 if (rc < 0) {
47 DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n", 50 DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n",
48 hwirq, mapping, rc); 51 hwirq, mapping, rc);
49 return IRQ_NONE; 52 break;
50 } 53 }
51 54
52 interrupts &= ~(1 << hwirq); 55 interrupts &= ~(1 << hwirq);
53 } 56 }
54 57
55 return IRQ_HANDLED; 58 chained_irq_exit(chip, desc);
56} 59}
57 60
58static void dpu_mdss_irq_mask(struct irq_data *irqd) 61static void dpu_mdss_irq_mask(struct irq_data *irqd)
@@ -83,16 +86,16 @@ static struct irq_chip dpu_mdss_irq_chip = {
83 .irq_unmask = dpu_mdss_irq_unmask, 86 .irq_unmask = dpu_mdss_irq_unmask,
84}; 87};
85 88
89static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key;
90
86static int dpu_mdss_irqdomain_map(struct irq_domain *domain, 91static int dpu_mdss_irqdomain_map(struct irq_domain *domain,
87 unsigned int irq, irq_hw_number_t hwirq) 92 unsigned int irq, irq_hw_number_t hwirq)
88{ 93{
89 struct dpu_mdss *dpu_mdss = domain->host_data; 94 struct dpu_mdss *dpu_mdss = domain->host_data;
90 int ret;
91 95
96 irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key);
92 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq); 97 irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq);
93 ret = irq_set_chip_data(irq, dpu_mdss); 98 return irq_set_chip_data(irq, dpu_mdss);
94
95 return ret;
96} 99}
97 100
98static const struct irq_domain_ops dpu_mdss_irqdomain_ops = { 101static const struct irq_domain_ops dpu_mdss_irqdomain_ops = {
@@ -159,11 +162,13 @@ static void dpu_mdss_destroy(struct drm_device *dev)
159 struct msm_drm_private *priv = dev->dev_private; 162 struct msm_drm_private *priv = dev->dev_private;
160 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); 163 struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss);
161 struct dss_module_power *mp = &dpu_mdss->mp; 164 struct dss_module_power *mp = &dpu_mdss->mp;
165 int irq;
162 166
163 pm_runtime_suspend(dev->dev); 167 pm_runtime_suspend(dev->dev);
164 pm_runtime_disable(dev->dev); 168 pm_runtime_disable(dev->dev);
165 _dpu_mdss_irq_domain_fini(dpu_mdss); 169 _dpu_mdss_irq_domain_fini(dpu_mdss);
166 free_irq(platform_get_irq(pdev, 0), dpu_mdss); 170 irq = platform_get_irq(pdev, 0);
171 irq_set_chained_handler_and_data(irq, NULL, NULL);
167 msm_dss_put_clk(mp->clk_config, mp->num_clk); 172 msm_dss_put_clk(mp->clk_config, mp->num_clk);
168 devm_kfree(&pdev->dev, mp->clk_config); 173 devm_kfree(&pdev->dev, mp->clk_config);
169 174
@@ -187,6 +192,7 @@ int dpu_mdss_init(struct drm_device *dev)
187 struct dpu_mdss *dpu_mdss; 192 struct dpu_mdss *dpu_mdss;
188 struct dss_module_power *mp; 193 struct dss_module_power *mp;
189 int ret = 0; 194 int ret = 0;
195 int irq;
190 196
191 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL); 197 dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL);
192 if (!dpu_mdss) 198 if (!dpu_mdss)
@@ -219,12 +225,12 @@ int dpu_mdss_init(struct drm_device *dev)
219 if (ret) 225 if (ret)
220 goto irq_domain_error; 226 goto irq_domain_error;
221 227
222 ret = request_irq(platform_get_irq(pdev, 0), 228 irq = platform_get_irq(pdev, 0);
223 dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss); 229 if (irq < 0)
224 if (ret) {
225 DPU_ERROR("failed to init irq: %d\n", ret);
226 goto irq_error; 230 goto irq_error;
227 } 231
232 irq_set_chained_handler_and_data(irq, dpu_mdss_irq,
233 dpu_mdss);
228 234
229 pm_runtime_enable(dev->dev); 235 pm_runtime_enable(dev->dev);
230 236