drm/meson: Support Overlay plane for video rendering

The Amlogic Meson GX SoCs support an Overlay plane behind the primary
plane for video rendering.

This Overlay plane support various YUV layouts :
- YUYV
- NV12 / NV21
- YUV444 / 422 / 420 / 411 / 410

The scaler supports a wide range of scaling ratios, but for simplicity,
plane atomic check limits the scaling from x5 to /5 in vertical and
horizontal scaling.

The z-order is fixed and always behind the primary plane and cannot be changed.

The scaling parameter algorithm was taken from the Amlogic vendor kernel
code and rewritten to match the atomic universal plane requirements.

The video rendering using this overlay plane support has been tested using
the new Kodi DRM-KMS Prime rendering path along the in-review V4L2 Mem2Mem
Hardware Video Decoder up to 3840x2160 NV12 frames on various display modes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Maxime Jourdan <mjourdan@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1541497202-20570-2-git-send-email-narmstrong@baylibre.com

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/gpu/drm/meson/meson_canvas.c b/drivers/gpu/drm/meson/meson_canvas.c
index 08f6073d967e..5de11aa7c775 100644
--- a/drivers/gpu/drm/meson/meson_canvas.c
+++ b/drivers/gpu/drm/meson/meson_canvas.c
@@ -39,6 +39,7 @@
 #define CANVAS_WIDTH_HBIT       0
 #define CANVAS_HEIGHT_BIT       9
 #define CANVAS_BLKMODE_BIT      24
+#define CANVAS_ENDIAN_BIT       26
 #define DMC_CAV_LUT_ADDR        0x50 /* 0x14 offset in data sheet */
 #define CANVAS_LUT_WR_EN        (0x2 << 8)
 #define CANVAS_LUT_RD_EN        (0x1 << 8)
@@ -47,7 +48,8 @@ void meson_canvas_setup(struct meson_drm *priv,
                         uint32_t canvas_index, uint32_t addr,
                         uint32_t stride, uint32_t height,
                         unsigned int wrap,
-                        unsigned int blkmode)
+                        unsigned int blkmode,
+                        unsigned int endian)
 {
         unsigned int val;
 
@@ -60,7 +62,8 @@ void meson_canvas_setup(struct meson_drm *priv,
                                                 CANVAS_WIDTH_HBIT) |
                 (height << CANVAS_HEIGHT_BIT) |
                 (wrap << 22) |
-                (blkmode << CANVAS_BLKMODE_BIT));
+                (blkmode << CANVAS_BLKMODE_BIT) |
+                (endian << CANVAS_ENDIAN_BIT));
 
         regmap_write(priv->dmc, DMC_CAV_LUT_ADDR,
                         CANVAS_LUT_WR_EN | canvas_index);