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authorDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
committerDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
commit1d2add28edd268a8290801ccf46b37f6d5239cdb (patch)
tree534e967b692f816434c00de0893e1089d425ae92 /drivers/gpu/drm/imx/imx-tve.c
parentbb1dc08c94ead1b98e750caf535422f79363c1a2 (diff)
parent5e501ed7253b369a8a9ec553c35238a3d6808f28 (diff)
Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm changes to use media bus formats and LDB drm_panel support - Add media bus formats needed by imx-drm - Switch to use media bus formats to describe the pixel format on the internal parallel bus between display interface and encoders - Some preparations for TV Output via TVEv2 on i.MX5 - Add drm_panel support to the i.MX LVDS driver, allow to determine the bus pixel format from the panel descriptor. * tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux: drm/imx: imx-ldb: allow to determine bus format from the connected panel drm/imx: imx-ldb: reset display clock input when disabling LVDS drm/imx: imx-ldb: add drm_panel support drm/imx: consolidate bus format variable names drm/imx: switch to use media bus formats Add RGB666_1X24_CPADHI media bus format Add YUV8_1X24 media bus format Add BGR888_1X24 and GBR888_1X24 media bus formats Add LVDS RGB media bus formats Add RGB444_1X12 and RGB565_1X16 media bus formats drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 drm/imx: Add support for interlaced scanout
Diffstat (limited to 'drivers/gpu/drm/imx/imx-tve.c')
-rw-r--r--drivers/gpu/drm/imx/imx-tve.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index 4216e479a9be..214eceefc981 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -301,11 +301,11 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
301 301
302 switch (tve->mode) { 302 switch (tve->mode) {
303 case TVE_MODE_VGA: 303 case TVE_MODE_VGA:
304 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, 304 imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_YUV8_1X24,
305 tve->hsync_pin, tve->vsync_pin); 305 tve->hsync_pin, tve->vsync_pin);
306 break; 306 break;
307 case TVE_MODE_TVOUT: 307 case TVE_MODE_TVOUT:
308 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444); 308 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24);
309 break; 309 break;
310 } 310 }
311} 311}