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authorChris Wilson <chris@chris-wilson.co.uk>2016-07-13 04:10:38 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2016-07-14 10:24:34 -0400
commitfb7404e81555b670e44fed6a95c277fe0214f540 (patch)
tree3505208b1763db7ee87a40ab026d08f47128cba3 /drivers/gpu/drm/i915
parentb7137e0cf1e55b5b0cb88fbd85425a1bc0d24c3a (diff)
drm/i915: Hide gen6_update_ring_freq()
This function is no longer used outside of intel_pm.c so we can stop exposing it and rename the __gen6_update_ring_freq() to take its place. Suggested-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1468397438-21226-8-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h1
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c18
2 files changed, 4 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c036dfdffe0d..57738bae1a28 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1695,7 +1695,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1695void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv); 1695void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1696void intel_disable_gt_powersave(struct drm_i915_private *dev_priv); 1696void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1697void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv); 1697void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1698void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1699void gen6_rps_busy(struct drm_i915_private *dev_priv); 1698void gen6_rps_busy(struct drm_i915_private *dev_priv);
1700void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); 1699void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1701void gen6_rps_idle(struct drm_i915_private *dev_priv); 1700void gen6_rps_idle(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c77ec106a93c..fa6b341c2792 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5436,7 +5436,7 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5436 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5436 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5437} 5437}
5438 5438
5439static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv) 5439static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5440{ 5440{
5441 int min_freq = 15; 5441 int min_freq = 15;
5442 unsigned int gpu_freq; 5442 unsigned int gpu_freq;
@@ -5520,16 +5520,6 @@ static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5520 } 5520 }
5521} 5521}
5522 5522
5523void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5524{
5525 if (!HAS_CORE_RING_FREQ(dev_priv))
5526 return;
5527
5528 mutex_lock(&dev_priv->rps.hw_lock);
5529 __gen6_update_ring_freq(dev_priv);
5530 mutex_unlock(&dev_priv->rps.hw_lock);
5531}
5532
5533static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5523static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5534{ 5524{
5535 u32 val, rp0; 5525 u32 val, rp0;
@@ -6624,13 +6614,13 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6624 gen9_enable_rc6(dev_priv); 6614 gen9_enable_rc6(dev_priv);
6625 gen9_enable_rps(dev_priv); 6615 gen9_enable_rps(dev_priv);
6626 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 6616 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6627 __gen6_update_ring_freq(dev_priv); 6617 gen6_update_ring_freq(dev_priv);
6628 } else if (IS_BROADWELL(dev_priv)) { 6618 } else if (IS_BROADWELL(dev_priv)) {
6629 gen8_enable_rps(dev_priv); 6619 gen8_enable_rps(dev_priv);
6630 __gen6_update_ring_freq(dev_priv); 6620 gen6_update_ring_freq(dev_priv);
6631 } else if (INTEL_GEN(dev_priv) >= 6) { 6621 } else if (INTEL_GEN(dev_priv) >= 6) {
6632 gen6_enable_rps(dev_priv); 6622 gen6_enable_rps(dev_priv);
6633 __gen6_update_ring_freq(dev_priv); 6623 gen6_update_ring_freq(dev_priv);
6634 } else if (IS_IRONLAKE_M(dev_priv)) { 6624 } else if (IS_IRONLAKE_M(dev_priv)) {
6635 ironlake_enable_drps(dev_priv); 6625 ironlake_enable_drps(dev_priv);
6636 intel_init_emon(dev_priv); 6626 intel_init_emon(dev_priv);