diff options
| author | Lyude Paul <lyude@redhat.com> | 2019-01-15 15:08:00 -0500 |
|---|---|---|
| committer | Lyude Paul <lyude@redhat.com> | 2019-01-15 16:10:43 -0500 |
| commit | 96550555a78ca3c9fda4b358549a5622810fe32c (patch) | |
| tree | 3eab6ac11b6e0554506588b61b91d506997deb02 /drivers/gpu/drm/i915 | |
| parent | 81c5a2c796493d63693dae9c23aeee451695bae7 (diff) | |
drm/i915: Pass down rc in intel_encoder->compute_config()
Something that I completely missed when implementing the new MST VCPI
atomic helpers is that with those helpers, there's technically a chance
of us having to grab additional modeset locks in ->compute_config() and
furthermore, that means we have the potential to hit a normal modeset
deadlock. However, because ->compute_config() only returns a bool this
means we can't return -EDEADLK when we need to drop locks and try again
which means we end up just failing the atomic check permanently. Whoops.
So, fix this by modifying ->compute_config() to pass down an actual
error code instead of a bool so that the atomic check can be restarted
on modeset deadlocks.
Thanks to Ville Syrjälä for pointing this out!
Changes since v1:
* Add some newlines
* Return only -EINVAL from hsw_crt_compute_config()
* Propogate return code from intel_dp_compute_dsc_params()
* Change all of the intel_dp_compute_link_config*() variants
* Don't miss if (hdmi_port_clock_valid()) branch in
intel_hdmi_compute_config()
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: eceae1472467 ("drm/dp_mst: Start tracking per-port VCPI allocations")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109320
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190115200800.3121-1-lyude@redhat.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/icl_dsi.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 35 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 71 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp_mst.c | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dvo.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_tv.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/vlv_dsi.c | 14 |
13 files changed, 122 insertions, 112 deletions
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 4dd793b78996..d9dcee4ec51f 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c | |||
| @@ -1178,9 +1178,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, | |||
| 1178 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); | 1178 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); |
| 1179 | } | 1179 | } |
| 1180 | 1180 | ||
| 1181 | static bool gen11_dsi_compute_config(struct intel_encoder *encoder, | 1181 | static int gen11_dsi_compute_config(struct intel_encoder *encoder, |
| 1182 | struct intel_crtc_state *pipe_config, | 1182 | struct intel_crtc_state *pipe_config, |
| 1183 | struct drm_connector_state *conn_state) | 1183 | struct drm_connector_state *conn_state) |
| 1184 | { | 1184 | { |
| 1185 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | 1185 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
| 1186 | base); | 1186 | base); |
| @@ -1205,7 +1205,7 @@ static bool gen11_dsi_compute_config(struct intel_encoder *encoder, | |||
| 1205 | pipe_config->clock_set = true; | 1205 | pipe_config->clock_set = true; |
| 1206 | pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; | 1206 | pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; |
| 1207 | 1207 | ||
| 1208 | return true; | 1208 | return 0; |
| 1209 | } | 1209 | } |
| 1210 | 1210 | ||
| 1211 | static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder, | 1211 | static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder, |
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 68f2fb89ece3..2e0fd9927db2 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
| @@ -344,51 +344,52 @@ intel_crt_mode_valid(struct drm_connector *connector, | |||
| 344 | return MODE_OK; | 344 | return MODE_OK; |
| 345 | } | 345 | } |
| 346 | 346 | ||
| 347 | static bool intel_crt_compute_config(struct intel_encoder *encoder, | 347 | static int intel_crt_compute_config(struct intel_encoder *encoder, |
| 348 | struct intel_crtc_state *pipe_config, | 348 | struct intel_crtc_state *pipe_config, |
| 349 | struct drm_connector_state *conn_state) | 349 | struct drm_connector_state *conn_state) |
| 350 | { | 350 | { |
| 351 | struct drm_display_mode *adjusted_mode = | 351 | struct drm_display_mode *adjusted_mode = |
| 352 | &pipe_config->base.adjusted_mode; | 352 | &pipe_config->base.adjusted_mode; |
| 353 | 353 | ||
| 354 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 354 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 355 | return false; | 355 | return -EINVAL; |
| 356 | 356 | ||
| 357 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 357 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 358 | return true; | 358 | |
| 359 | return 0; | ||
| 359 | } | 360 | } |
| 360 | 361 | ||
| 361 | static bool pch_crt_compute_config(struct intel_encoder *encoder, | 362 | static int pch_crt_compute_config(struct intel_encoder *encoder, |
| 362 | struct intel_crtc_state *pipe_config, | 363 | struct intel_crtc_state *pipe_config, |
| 363 | struct drm_connector_state *conn_state) | 364 | struct drm_connector_state *conn_state) |
| 364 | { | 365 | { |
| 365 | struct drm_display_mode *adjusted_mode = | 366 | struct drm_display_mode *adjusted_mode = |
| 366 | &pipe_config->base.adjusted_mode; | 367 | &pipe_config->base.adjusted_mode; |
| 367 | 368 | ||
| 368 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 369 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 369 | return false; | 370 | return -EINVAL; |
| 370 | 371 | ||
| 371 | pipe_config->has_pch_encoder = true; | 372 | pipe_config->has_pch_encoder = true; |
| 372 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 373 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 373 | 374 | ||
| 374 | return true; | 375 | return 0; |
| 375 | } | 376 | } |
| 376 | 377 | ||
| 377 | static bool hsw_crt_compute_config(struct intel_encoder *encoder, | 378 | static int hsw_crt_compute_config(struct intel_encoder *encoder, |
| 378 | struct intel_crtc_state *pipe_config, | 379 | struct intel_crtc_state *pipe_config, |
| 379 | struct drm_connector_state *conn_state) | 380 | struct drm_connector_state *conn_state) |
| 380 | { | 381 | { |
| 381 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | 382 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 382 | struct drm_display_mode *adjusted_mode = | 383 | struct drm_display_mode *adjusted_mode = |
| 383 | &pipe_config->base.adjusted_mode; | 384 | &pipe_config->base.adjusted_mode; |
| 384 | 385 | ||
| 385 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 386 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 386 | return false; | 387 | return -EINVAL; |
| 387 | 388 | ||
| 388 | /* HSW/BDW FDI limited to 4k */ | 389 | /* HSW/BDW FDI limited to 4k */ |
| 389 | if (adjusted_mode->crtc_hdisplay > 4096 || | 390 | if (adjusted_mode->crtc_hdisplay > 4096 || |
| 390 | adjusted_mode->crtc_hblank_start > 4096) | 391 | adjusted_mode->crtc_hblank_start > 4096) |
| 391 | return false; | 392 | return -EINVAL; |
| 392 | 393 | ||
| 393 | pipe_config->has_pch_encoder = true; | 394 | pipe_config->has_pch_encoder = true; |
| 394 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 395 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| @@ -397,7 +398,7 @@ static bool hsw_crt_compute_config(struct intel_encoder *encoder, | |||
| 397 | if (HAS_PCH_LPT(dev_priv)) { | 398 | if (HAS_PCH_LPT(dev_priv)) { |
| 398 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { | 399 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
| 399 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | 400 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); |
| 400 | return false; | 401 | return -EINVAL; |
| 401 | } | 402 | } |
| 402 | 403 | ||
| 403 | pipe_config->pipe_bpp = 24; | 404 | pipe_config->pipe_bpp = 24; |
| @@ -406,7 +407,7 @@ static bool hsw_crt_compute_config(struct intel_encoder *encoder, | |||
| 406 | /* FDI must always be 2.7 GHz */ | 407 | /* FDI must always be 2.7 GHz */ |
| 407 | pipe_config->port_clock = 135000 * 2; | 408 | pipe_config->port_clock = 135000 * 2; |
| 408 | 409 | ||
| 409 | return true; | 410 | return 0; |
| 410 | } | 411 | } |
| 411 | 412 | ||
| 412 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) | 413 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f3e1d6a0b7dd..fd06d1fd39d3 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c | |||
| @@ -3875,9 +3875,9 @@ intel_ddi_compute_output_type(struct intel_encoder *encoder, | |||
| 3875 | } | 3875 | } |
| 3876 | } | 3876 | } |
| 3877 | 3877 | ||
| 3878 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, | 3878 | static int intel_ddi_compute_config(struct intel_encoder *encoder, |
| 3879 | struct intel_crtc_state *pipe_config, | 3879 | struct intel_crtc_state *pipe_config, |
| 3880 | struct drm_connector_state *conn_state) | 3880 | struct drm_connector_state *conn_state) |
| 3881 | { | 3881 | { |
| 3882 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | 3882 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 3883 | enum port port = encoder->port; | 3883 | enum port port = encoder->port; |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 20beb1977a27..52c63135bc65 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -11517,10 +11517,13 @@ encoder_retry: | |||
| 11517 | continue; | 11517 | continue; |
| 11518 | 11518 | ||
| 11519 | encoder = to_intel_encoder(connector_state->best_encoder); | 11519 | encoder = to_intel_encoder(connector_state->best_encoder); |
| 11520 | 11520 | ret = encoder->compute_config(encoder, pipe_config, | |
| 11521 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { | 11521 | connector_state); |
| 11522 | DRM_DEBUG_KMS("Encoder config failure\n"); | 11522 | if (ret < 0) { |
| 11523 | return -EINVAL; | 11523 | if (ret != -EDEADLK) |
| 11524 | DRM_DEBUG_KMS("Encoder config failure: %d\n", | ||
| 11525 | ret); | ||
| 11526 | return ret; | ||
| 11524 | } | 11527 | } |
| 11525 | } | 11528 | } |
| 11526 | 11529 | ||
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fdd2cbc56fa3..d18b72b5f0b8 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
| @@ -1808,7 +1808,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, | |||
| 1808 | } | 1808 | } |
| 1809 | 1809 | ||
| 1810 | /* Optimize link config in order: max bpp, min clock, min lanes */ | 1810 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
| 1811 | static bool | 1811 | static int |
| 1812 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, | 1812 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
| 1813 | struct intel_crtc_state *pipe_config, | 1813 | struct intel_crtc_state *pipe_config, |
| 1814 | const struct link_config_limits *limits) | 1814 | const struct link_config_limits *limits) |
| @@ -1834,17 +1834,17 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, | |||
| 1834 | pipe_config->pipe_bpp = bpp; | 1834 | pipe_config->pipe_bpp = bpp; |
| 1835 | pipe_config->port_clock = link_clock; | 1835 | pipe_config->port_clock = link_clock; |
| 1836 | 1836 | ||
| 1837 | return true; | 1837 | return 0; |
| 1838 | } | 1838 | } |
| 1839 | } | 1839 | } |
| 1840 | } | 1840 | } |
| 1841 | } | 1841 | } |
| 1842 | 1842 | ||
| 1843 | return false; | 1843 | return -EINVAL; |
| 1844 | } | 1844 | } |
| 1845 | 1845 | ||
| 1846 | /* Optimize link config in order: max bpp, min lanes, min clock */ | 1846 | /* Optimize link config in order: max bpp, min lanes, min clock */ |
| 1847 | static bool | 1847 | static int |
| 1848 | intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, | 1848 | intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, |
| 1849 | struct intel_crtc_state *pipe_config, | 1849 | struct intel_crtc_state *pipe_config, |
| 1850 | const struct link_config_limits *limits) | 1850 | const struct link_config_limits *limits) |
| @@ -1870,13 +1870,13 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, | |||
| 1870 | pipe_config->pipe_bpp = bpp; | 1870 | pipe_config->pipe_bpp = bpp; |
| 1871 | pipe_config->port_clock = link_clock; | 1871 | pipe_config->port_clock = link_clock; |
| 1872 | 1872 | ||
| 1873 | return true; | 1873 | return 0; |
| 1874 | } | 1874 | } |
| 1875 | } | 1875 | } |
| 1876 | } | 1876 | } |
| 1877 | } | 1877 | } |
| 1878 | 1878 | ||
| 1879 | return false; | 1879 | return -EINVAL; |
| 1880 | } | 1880 | } |
| 1881 | 1881 | ||
| 1882 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) | 1882 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
| @@ -1894,19 +1894,20 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) | |||
| 1894 | return 0; | 1894 | return 0; |
| 1895 | } | 1895 | } |
| 1896 | 1896 | ||
| 1897 | static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, | 1897 | static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
| 1898 | struct intel_crtc_state *pipe_config, | 1898 | struct intel_crtc_state *pipe_config, |
| 1899 | struct drm_connector_state *conn_state, | 1899 | struct drm_connector_state *conn_state, |
| 1900 | struct link_config_limits *limits) | 1900 | struct link_config_limits *limits) |
| 1901 | { | 1901 | { |
| 1902 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | 1902 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1903 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | 1903 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
| 1904 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | 1904 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
| 1905 | u8 dsc_max_bpc; | 1905 | u8 dsc_max_bpc; |
| 1906 | int pipe_bpp; | 1906 | int pipe_bpp; |
| 1907 | int ret; | ||
| 1907 | 1908 | ||
| 1908 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) | 1909 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
| 1909 | return false; | 1910 | return -EINVAL; |
| 1910 | 1911 | ||
| 1911 | dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC, | 1912 | dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC, |
| 1912 | conn_state->max_requested_bpc); | 1913 | conn_state->max_requested_bpc); |
| @@ -1914,7 +1915,7 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, | |||
| 1914 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); | 1915 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); |
| 1915 | if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) { | 1916 | if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) { |
| 1916 | DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); | 1917 | DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); |
| 1917 | return false; | 1918 | return -EINVAL; |
| 1918 | } | 1919 | } |
| 1919 | 1920 | ||
| 1920 | /* | 1921 | /* |
| @@ -1948,7 +1949,7 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, | |||
| 1948 | adjusted_mode->crtc_hdisplay); | 1949 | adjusted_mode->crtc_hdisplay); |
| 1949 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { | 1950 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { |
| 1950 | DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); | 1951 | DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); |
| 1951 | return false; | 1952 | return -EINVAL; |
| 1952 | } | 1953 | } |
| 1953 | pipe_config->dsc_params.compressed_bpp = min_t(u16, | 1954 | pipe_config->dsc_params.compressed_bpp = min_t(u16, |
| 1954 | dsc_max_output_bpp >> 4, | 1955 | dsc_max_output_bpp >> 4, |
| @@ -1965,16 +1966,19 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, | |||
| 1965 | pipe_config->dsc_params.dsc_split = true; | 1966 | pipe_config->dsc_params.dsc_split = true; |
| 1966 | } else { | 1967 | } else { |
| 1967 | DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); | 1968 | DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); |
| 1968 | return false; | 1969 | return -EINVAL; |
| 1969 | } | 1970 | } |
| 1970 | } | 1971 | } |
| 1971 | if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) { | 1972 | |
| 1973 | ret = intel_dp_compute_dsc_params(intel_dp, pipe_config); | ||
| 1974 | if (ret < 0) { | ||
| 1972 | DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " | 1975 | DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " |
| 1973 | "Compressed BPP = %d\n", | 1976 | "Compressed BPP = %d\n", |
| 1974 | pipe_config->pipe_bpp, | 1977 | pipe_config->pipe_bpp, |
| 1975 | pipe_config->dsc_params.compressed_bpp); | 1978 | pipe_config->dsc_params.compressed_bpp); |
| 1976 | return false; | 1979 | return ret; |
| 1977 | } | 1980 | } |
| 1981 | |||
| 1978 | pipe_config->dsc_params.compression_enable = true; | 1982 | pipe_config->dsc_params.compression_enable = true; |
| 1979 | DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " | 1983 | DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " |
| 1980 | "Compressed Bpp = %d Slice Count = %d\n", | 1984 | "Compressed Bpp = %d Slice Count = %d\n", |
| @@ -1982,10 +1986,10 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, | |||
| 1982 | pipe_config->dsc_params.compressed_bpp, | 1986 | pipe_config->dsc_params.compressed_bpp, |
| 1983 | pipe_config->dsc_params.slice_count); | 1987 | pipe_config->dsc_params.slice_count); |
| 1984 | 1988 | ||
| 1985 | return true; | 1989 | return 0; |
| 1986 | } | 1990 | } |
| 1987 | 1991 | ||
| 1988 | static bool | 1992 | static int |
| 1989 | intel_dp_compute_link_config(struct intel_encoder *encoder, | 1993 | intel_dp_compute_link_config(struct intel_encoder *encoder, |
| 1990 | struct intel_crtc_state *pipe_config, | 1994 | struct intel_crtc_state *pipe_config, |
| 1991 | struct drm_connector_state *conn_state) | 1995 | struct drm_connector_state *conn_state) |
| @@ -1994,7 +1998,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, | |||
| 1994 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | 1998 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1995 | struct link_config_limits limits; | 1999 | struct link_config_limits limits; |
| 1996 | int common_len; | 2000 | int common_len; |
| 1997 | bool ret; | 2001 | int ret; |
| 1998 | 2002 | ||
| 1999 | common_len = intel_dp_common_len_rate_limit(intel_dp, | 2003 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
| 2000 | intel_dp->max_link_rate); | 2004 | intel_dp->max_link_rate); |
| @@ -2051,10 +2055,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, | |||
| 2051 | &limits); | 2055 | &limits); |
| 2052 | 2056 | ||
| 2053 | /* enable compression if the mode doesn't fit available BW */ | 2057 | /* enable compression if the mode doesn't fit available BW */ |
| 2054 | if (!ret) { | 2058 | if (ret) { |
| 2055 | if (!intel_dp_dsc_compute_config(intel_dp, pipe_config, | 2059 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, |
| 2056 | conn_state, &limits)) | 2060 | conn_state, &limits); |
| 2057 | return false; | 2061 | if (ret < 0) |
| 2062 | return ret; | ||
| 2058 | } | 2063 | } |
| 2059 | 2064 | ||
| 2060 | if (pipe_config->dsc_params.compression_enable) { | 2065 | if (pipe_config->dsc_params.compression_enable) { |
| @@ -2079,10 +2084,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, | |||
| 2079 | intel_dp_max_data_rate(pipe_config->port_clock, | 2084 | intel_dp_max_data_rate(pipe_config->port_clock, |
| 2080 | pipe_config->lane_count)); | 2085 | pipe_config->lane_count)); |
| 2081 | } | 2086 | } |
| 2082 | return true; | 2087 | return 0; |
| 2083 | } | 2088 | } |
| 2084 | 2089 | ||
| 2085 | bool | 2090 | int |
| 2086 | intel_dp_compute_config(struct intel_encoder *encoder, | 2091 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 2087 | struct intel_crtc_state *pipe_config, | 2092 | struct intel_crtc_state *pipe_config, |
| 2088 | struct drm_connector_state *conn_state) | 2093 | struct drm_connector_state *conn_state) |
| @@ -2098,6 +2103,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
| 2098 | to_intel_digital_connector_state(conn_state); | 2103 | to_intel_digital_connector_state(conn_state); |
| 2099 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, | 2104 | bool constant_n = drm_dp_has_quirk(&intel_dp->desc, |
| 2100 | DP_DPCD_QUIRK_CONSTANT_N); | 2105 | DP_DPCD_QUIRK_CONSTANT_N); |
| 2106 | int ret; | ||
| 2101 | 2107 | ||
| 2102 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) | 2108 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
| 2103 | pipe_config->has_pch_encoder = true; | 2109 | pipe_config->has_pch_encoder = true; |
| @@ -2119,8 +2125,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
| 2119 | adjusted_mode); | 2125 | adjusted_mode); |
| 2120 | 2126 | ||
| 2121 | if (INTEL_GEN(dev_priv) >= 9) { | 2127 | if (INTEL_GEN(dev_priv) >= 9) { |
| 2122 | int ret; | ||
| 2123 | |||
| 2124 | ret = skl_update_scaler_crtc(pipe_config); | 2128 | ret = skl_update_scaler_crtc(pipe_config); |
| 2125 | if (ret) | 2129 | if (ret) |
| 2126 | return ret; | 2130 | return ret; |
| @@ -2135,20 +2139,21 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
| 2135 | } | 2139 | } |
| 2136 | 2140 | ||
| 2137 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 2141 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 2138 | return false; | 2142 | return -EINVAL; |
| 2139 | 2143 | ||
| 2140 | if (HAS_GMCH_DISPLAY(dev_priv) && | 2144 | if (HAS_GMCH_DISPLAY(dev_priv) && |
| 2141 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | 2145 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 2142 | return false; | 2146 | return -EINVAL; |
| 2143 | 2147 | ||
| 2144 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | 2148 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 2145 | return false; | 2149 | return -EINVAL; |
| 2146 | 2150 | ||
| 2147 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && | 2151 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
| 2148 | intel_dp_supports_fec(intel_dp, pipe_config); | 2152 | intel_dp_supports_fec(intel_dp, pipe_config); |
| 2149 | 2153 | ||
| 2150 | if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state)) | 2154 | ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
| 2151 | return false; | 2155 | if (ret < 0) |
| 2156 | return ret; | ||
| 2152 | 2157 | ||
| 2153 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { | 2158 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
| 2154 | /* | 2159 | /* |
| @@ -2196,7 +2201,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
| 2196 | 2201 | ||
| 2197 | intel_psr_compute_config(intel_dp, pipe_config); | 2202 | intel_psr_compute_config(intel_dp, pipe_config); |
| 2198 | 2203 | ||
| 2199 | return true; | 2204 | return 0; |
| 2200 | } | 2205 | } |
| 2201 | 2206 | ||
| 2202 | void intel_dp_set_link_params(struct intel_dp *intel_dp, | 2207 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index c8e2215628e6..5899debe2184 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c | |||
| @@ -30,9 +30,9 @@ | |||
| 30 | #include <drm/drm_crtc_helper.h> | 30 | #include <drm/drm_crtc_helper.h> |
| 31 | #include <drm/drm_edid.h> | 31 | #include <drm/drm_edid.h> |
| 32 | 32 | ||
| 33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | 33 | static int intel_dp_mst_compute_config(struct intel_encoder *encoder, |
| 34 | struct intel_crtc_state *pipe_config, | 34 | struct intel_crtc_state *pipe_config, |
| 35 | struct drm_connector_state *conn_state) | 35 | struct drm_connector_state *conn_state) |
| 36 | { | 36 | { |
| 37 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | 37 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 38 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | 38 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); |
| @@ -53,7 +53,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
| 53 | DP_DPCD_QUIRK_CONSTANT_N); | 53 | DP_DPCD_QUIRK_CONSTANT_N); |
| 54 | 54 | ||
| 55 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 55 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 56 | return false; | 56 | return -EINVAL; |
| 57 | 57 | ||
| 58 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 58 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 59 | pipe_config->has_pch_encoder = false; | 59 | pipe_config->has_pch_encoder = false; |
| @@ -90,7 +90,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
| 90 | if (slots < 0) { | 90 | if (slots < 0) { |
| 91 | DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", | 91 | DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", |
| 92 | slots); | 92 | slots); |
| 93 | return false; | 93 | return slots; |
| 94 | } | 94 | } |
| 95 | } | 95 | } |
| 96 | 96 | ||
| @@ -108,7 +108,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |||
| 108 | 108 | ||
| 109 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); | 109 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |
| 110 | 110 | ||
| 111 | return true; | 111 | return 0; |
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | static int | 114 | static int |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index a3252064b8d2..19d9abd2666e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
| @@ -222,9 +222,9 @@ struct intel_encoder { | |||
| 222 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, | 222 | enum intel_output_type (*compute_output_type)(struct intel_encoder *, |
| 223 | struct intel_crtc_state *, | 223 | struct intel_crtc_state *, |
| 224 | struct drm_connector_state *); | 224 | struct drm_connector_state *); |
| 225 | bool (*compute_config)(struct intel_encoder *, | 225 | int (*compute_config)(struct intel_encoder *, |
| 226 | struct intel_crtc_state *, | 226 | struct intel_crtc_state *, |
| 227 | struct drm_connector_state *); | 227 | struct drm_connector_state *); |
| 228 | void (*pre_pll_enable)(struct intel_encoder *, | 228 | void (*pre_pll_enable)(struct intel_encoder *, |
| 229 | const struct intel_crtc_state *, | 229 | const struct intel_crtc_state *, |
| 230 | const struct drm_connector_state *); | 230 | const struct drm_connector_state *); |
| @@ -1806,9 +1806,9 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, | |||
| 1806 | void intel_dp_encoder_reset(struct drm_encoder *encoder); | 1806 | void intel_dp_encoder_reset(struct drm_encoder *encoder); |
| 1807 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); | 1807 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); |
| 1808 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | 1808 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| 1809 | bool intel_dp_compute_config(struct intel_encoder *encoder, | 1809 | int intel_dp_compute_config(struct intel_encoder *encoder, |
| 1810 | struct intel_crtc_state *pipe_config, | 1810 | struct intel_crtc_state *pipe_config, |
| 1811 | struct drm_connector_state *conn_state); | 1811 | struct drm_connector_state *conn_state); |
| 1812 | bool intel_dp_is_edp(struct intel_dp *intel_dp); | 1812 | bool intel_dp_is_edp(struct intel_dp *intel_dp); |
| 1813 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); | 1813 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
| 1814 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, | 1814 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| @@ -1966,9 +1966,9 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, | |||
| 1966 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | 1966 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| 1967 | struct intel_connector *intel_connector); | 1967 | struct intel_connector *intel_connector); |
| 1968 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | 1968 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| 1969 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | 1969 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1970 | struct intel_crtc_state *pipe_config, | 1970 | struct intel_crtc_state *pipe_config, |
| 1971 | struct drm_connector_state *conn_state); | 1971 | struct drm_connector_state *conn_state); |
| 1972 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, | 1972 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
| 1973 | struct drm_connector *connector, | 1973 | struct drm_connector *connector, |
| 1974 | bool high_tmds_clock_ratio, | 1974 | bool high_tmds_clock_ratio, |
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 0042a7f69387..17a16917e134 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c | |||
| @@ -235,9 +235,9 @@ intel_dvo_mode_valid(struct drm_connector *connector, | |||
| 235 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); | 235 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
| 236 | } | 236 | } |
| 237 | 237 | ||
| 238 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, | 238 | static int intel_dvo_compute_config(struct intel_encoder *encoder, |
| 239 | struct intel_crtc_state *pipe_config, | 239 | struct intel_crtc_state *pipe_config, |
| 240 | struct drm_connector_state *conn_state) | 240 | struct drm_connector_state *conn_state) |
| 241 | { | 241 | { |
| 242 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); | 242 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
| 243 | const struct drm_display_mode *fixed_mode = | 243 | const struct drm_display_mode *fixed_mode = |
| @@ -254,10 +254,11 @@ static bool intel_dvo_compute_config(struct intel_encoder *encoder, | |||
| 254 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | 254 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
| 255 | 255 | ||
| 256 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 256 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 257 | return false; | 257 | return -EINVAL; |
| 258 | 258 | ||
| 259 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 259 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 260 | return true; | 260 | |
| 261 | return 0; | ||
| 261 | } | 262 | } |
| 262 | 263 | ||
| 263 | static void intel_dvo_pre_enable(struct intel_encoder *encoder, | 264 | static void intel_dvo_pre_enable(struct intel_encoder *encoder, |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 55aeb97dd66d..1da7bb148fca 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
| @@ -1703,9 +1703,9 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |||
| 1703 | return true; | 1703 | return true; |
| 1704 | } | 1704 | } |
| 1705 | 1705 | ||
| 1706 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | 1706 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
| 1707 | struct intel_crtc_state *pipe_config, | 1707 | struct intel_crtc_state *pipe_config, |
| 1708 | struct drm_connector_state *conn_state) | 1708 | struct drm_connector_state *conn_state) |
| 1709 | { | 1709 | { |
| 1710 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | 1710 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
| 1711 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | 1711 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| @@ -1721,7 +1721,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
| 1721 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; | 1721 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
| 1722 | 1722 | ||
| 1723 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 1723 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1724 | return false; | 1724 | return -EINVAL; |
| 1725 | 1725 | ||
| 1726 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 1726 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 1727 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; | 1727 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
| @@ -1752,7 +1752,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
| 1752 | &clock_12bpc, &clock_10bpc, | 1752 | &clock_12bpc, &clock_10bpc, |
| 1753 | &clock_8bpc)) { | 1753 | &clock_8bpc)) { |
| 1754 | DRM_ERROR("Can't support YCBCR420 output\n"); | 1754 | DRM_ERROR("Can't support YCBCR420 output\n"); |
| 1755 | return false; | 1755 | return -EINVAL; |
| 1756 | } | 1756 | } |
| 1757 | } | 1757 | } |
| 1758 | 1758 | ||
| @@ -1802,7 +1802,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
| 1802 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, | 1802 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
| 1803 | false, force_dvi) != MODE_OK) { | 1803 | false, force_dvi) != MODE_OK) { |
| 1804 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | 1804 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
| 1805 | return false; | 1805 | return -EINVAL; |
| 1806 | } | 1806 | } |
| 1807 | 1807 | ||
| 1808 | /* Set user selected PAR to incoming mode's member */ | 1808 | /* Set user selected PAR to incoming mode's member */ |
| @@ -1821,7 +1821,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
| 1821 | } | 1821 | } |
| 1822 | } | 1822 | } |
| 1823 | 1823 | ||
| 1824 | return true; | 1824 | return 0; |
| 1825 | } | 1825 | } |
| 1826 | 1826 | ||
| 1827 | static void | 1827 | static void |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e6c5d985ea0a..3377d813dbb3 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
| @@ -379,9 +379,9 @@ intel_lvds_mode_valid(struct drm_connector *connector, | |||
| 379 | return MODE_OK; | 379 | return MODE_OK; |
| 380 | } | 380 | } |
| 381 | 381 | ||
| 382 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, | 382 | static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
| 383 | struct intel_crtc_state *pipe_config, | 383 | struct intel_crtc_state *pipe_config, |
| 384 | struct drm_connector_state *conn_state) | 384 | struct drm_connector_state *conn_state) |
| 385 | { | 385 | { |
| 386 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); | 386 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
| 387 | struct intel_lvds_encoder *lvds_encoder = | 387 | struct intel_lvds_encoder *lvds_encoder = |
| @@ -395,7 +395,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, | |||
| 395 | /* Should never happen!! */ | 395 | /* Should never happen!! */ |
| 396 | if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { | 396 | if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { |
| 397 | DRM_ERROR("Can't support LVDS on pipe A\n"); | 397 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
| 398 | return false; | 398 | return -EINVAL; |
| 399 | } | 399 | } |
| 400 | 400 | ||
| 401 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) | 401 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
| @@ -421,7 +421,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, | |||
| 421 | adjusted_mode); | 421 | adjusted_mode); |
| 422 | 422 | ||
| 423 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 423 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 424 | return false; | 424 | return -EINVAL; |
| 425 | 425 | ||
| 426 | if (HAS_PCH_SPLIT(dev_priv)) { | 426 | if (HAS_PCH_SPLIT(dev_priv)) { |
| 427 | pipe_config->has_pch_encoder = true; | 427 | pipe_config->has_pch_encoder = true; |
| @@ -440,7 +440,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, | |||
| 440 | * user's requested refresh rate. | 440 | * user's requested refresh rate. |
| 441 | */ | 441 | */ |
| 442 | 442 | ||
| 443 | return true; | 443 | return 0; |
| 444 | } | 444 | } |
| 445 | 445 | ||
| 446 | static enum drm_connector_status | 446 | static enum drm_connector_status |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 669fa9faad70..4a03b7f67dd5 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
| @@ -1108,9 +1108,9 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) | |||
| 1108 | pipe_config->clock_set = true; | 1108 | pipe_config->clock_set = true; |
| 1109 | } | 1109 | } |
| 1110 | 1110 | ||
| 1111 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, | 1111 | static int intel_sdvo_compute_config(struct intel_encoder *encoder, |
| 1112 | struct intel_crtc_state *pipe_config, | 1112 | struct intel_crtc_state *pipe_config, |
| 1113 | struct drm_connector_state *conn_state) | 1113 | struct drm_connector_state *conn_state) |
| 1114 | { | 1114 | { |
| 1115 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); | 1115 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1116 | struct intel_sdvo_connector_state *intel_sdvo_state = | 1116 | struct intel_sdvo_connector_state *intel_sdvo_state = |
| @@ -1135,7 +1135,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, | |||
| 1135 | */ | 1135 | */ |
| 1136 | if (IS_TV(intel_sdvo_connector)) { | 1136 | if (IS_TV(intel_sdvo_connector)) { |
| 1137 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | 1137 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
| 1138 | return false; | 1138 | return -EINVAL; |
| 1139 | 1139 | ||
| 1140 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, | 1140 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1141 | intel_sdvo_connector, | 1141 | intel_sdvo_connector, |
| @@ -1145,7 +1145,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, | |||
| 1145 | } else if (IS_LVDS(intel_sdvo_connector)) { | 1145 | } else if (IS_LVDS(intel_sdvo_connector)) { |
| 1146 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, | 1146 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
| 1147 | intel_sdvo_connector->base.panel.fixed_mode)) | 1147 | intel_sdvo_connector->base.panel.fixed_mode)) |
| 1148 | return false; | 1148 | return -EINVAL; |
| 1149 | 1149 | ||
| 1150 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, | 1150 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1151 | intel_sdvo_connector, | 1151 | intel_sdvo_connector, |
| @@ -1154,7 +1154,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, | |||
| 1154 | } | 1154 | } |
| 1155 | 1155 | ||
| 1156 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 1156 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1157 | return false; | 1157 | return -EINVAL; |
| 1158 | 1158 | ||
| 1159 | /* | 1159 | /* |
| 1160 | * Make the CRTC code factor in the SDVO pixel multiplier. The | 1160 | * Make the CRTC code factor in the SDVO pixel multiplier. The |
| @@ -1194,7 +1194,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder, | |||
| 1194 | if (intel_sdvo_connector->is_hdmi) | 1194 | if (intel_sdvo_connector->is_hdmi) |
| 1195 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; | 1195 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
| 1196 | 1196 | ||
| 1197 | return true; | 1197 | return 0; |
| 1198 | } | 1198 | } |
| 1199 | 1199 | ||
| 1200 | #define UPDATE_PROPERTY(input, NAME) \ | 1200 | #define UPDATE_PROPERTY(input, NAME) \ |
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 860f306a23ba..9bbe35a0f0f2 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c | |||
| @@ -870,7 +870,7 @@ intel_tv_get_config(struct intel_encoder *encoder, | |||
| 870 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; | 870 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
| 871 | } | 871 | } |
| 872 | 872 | ||
| 873 | static bool | 873 | static int |
| 874 | intel_tv_compute_config(struct intel_encoder *encoder, | 874 | intel_tv_compute_config(struct intel_encoder *encoder, |
| 875 | struct intel_crtc_state *pipe_config, | 875 | struct intel_crtc_state *pipe_config, |
| 876 | struct drm_connector_state *conn_state) | 876 | struct drm_connector_state *conn_state) |
| @@ -880,10 +880,10 @@ intel_tv_compute_config(struct intel_encoder *encoder, | |||
| 880 | &pipe_config->base.adjusted_mode; | 880 | &pipe_config->base.adjusted_mode; |
| 881 | 881 | ||
| 882 | if (!tv_mode) | 882 | if (!tv_mode) |
| 883 | return false; | 883 | return -EINVAL; |
| 884 | 884 | ||
| 885 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 885 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 886 | return false; | 886 | return -EINVAL; |
| 887 | 887 | ||
| 888 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; | 888 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 889 | adjusted_mode->crtc_clock = tv_mode->clock; | 889 | adjusted_mode->crtc_clock = tv_mode->clock; |
| @@ -898,7 +898,7 @@ intel_tv_compute_config(struct intel_encoder *encoder, | |||
| 898 | * or whether userspace is doing something stupid. | 898 | * or whether userspace is doing something stupid. |
| 899 | */ | 899 | */ |
| 900 | 900 | ||
| 901 | return true; | 901 | return 0; |
| 902 | } | 902 | } |
| 903 | 903 | ||
| 904 | static void | 904 | static void |
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index 361e962a7969..9fc8085f76dc 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c | |||
| @@ -257,9 +257,9 @@ static void band_gap_reset(struct drm_i915_private *dev_priv) | |||
| 257 | mutex_unlock(&dev_priv->sb_lock); | 257 | mutex_unlock(&dev_priv->sb_lock); |
| 258 | } | 258 | } |
| 259 | 259 | ||
| 260 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | 260 | static int intel_dsi_compute_config(struct intel_encoder *encoder, |
| 261 | struct intel_crtc_state *pipe_config, | 261 | struct intel_crtc_state *pipe_config, |
| 262 | struct drm_connector_state *conn_state) | 262 | struct drm_connector_state *conn_state) |
| 263 | { | 263 | { |
| 264 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | 264 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 265 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | 265 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
| @@ -285,7 +285,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |||
| 285 | } | 285 | } |
| 286 | 286 | ||
| 287 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | 287 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 288 | return false; | 288 | return -EINVAL; |
| 289 | 289 | ||
| 290 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ | 290 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
| 291 | adjusted_mode->flags = 0; | 291 | adjusted_mode->flags = 0; |
| @@ -303,16 +303,16 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |||
| 303 | 303 | ||
| 304 | ret = bxt_dsi_pll_compute(encoder, pipe_config); | 304 | ret = bxt_dsi_pll_compute(encoder, pipe_config); |
| 305 | if (ret) | 305 | if (ret) |
| 306 | return false; | 306 | return -EINVAL; |
| 307 | } else { | 307 | } else { |
| 308 | ret = vlv_dsi_pll_compute(encoder, pipe_config); | 308 | ret = vlv_dsi_pll_compute(encoder, pipe_config); |
| 309 | if (ret) | 309 | if (ret) |
| 310 | return false; | 310 | return -EINVAL; |
| 311 | } | 311 | } |
| 312 | 312 | ||
| 313 | pipe_config->clock_set = true; | 313 | pipe_config->clock_set = true; |
| 314 | 314 | ||
| 315 | return true; | 315 | return 0; |
| 316 | } | 316 | } |
| 317 | 317 | ||
| 318 | static bool glk_dsi_enable_io(struct intel_encoder *encoder) | 318 | static bool glk_dsi_enable_io(struct intel_encoder *encoder) |
