diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-11-14 11:53:59 -0500 |
---|---|---|
committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-11-14 12:58:26 -0500 |
commit | df0cd455e720e4c0a04a85eb8ec4d2dab2e37795 (patch) | |
tree | 97bfd1c4398cd626eb8865a608ba7b82a5903c13 /drivers/gpu/drm/i915/intel_sprite.c | |
parent | f22aa14352cc6f40fdb81cdb2e4f4f9d75613a37 (diff) |
drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup
Move the plane control register rotation setup away from the
coordinate munging code. This will result in neater looking
code once we add reflection support for CHV.
v2: Drop the BIT(), drop some usless parens,
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479142440-25283-3-git-send-email-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_sprite.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index ea85d27af217..7951b70bf792 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c | |||
@@ -427,6 +427,9 @@ vlv_update_plane(struct drm_plane *dplane, | |||
427 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | 427 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
428 | sprctl |= SP_TILED; | 428 | sprctl |= SP_TILED; |
429 | 429 | ||
430 | if (rotation & DRM_ROTATE_180) | ||
431 | sprctl |= SP_ROTATE_180; | ||
432 | |||
430 | /* Sizes are 0 based */ | 433 | /* Sizes are 0 based */ |
431 | src_w--; | 434 | src_w--; |
432 | src_h--; | 435 | src_h--; |
@@ -437,8 +440,6 @@ vlv_update_plane(struct drm_plane *dplane, | |||
437 | sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | 440 | sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); |
438 | 441 | ||
439 | if (rotation & DRM_ROTATE_180) { | 442 | if (rotation & DRM_ROTATE_180) { |
440 | sprctl |= SP_ROTATE_180; | ||
441 | |||
442 | x += src_w; | 443 | x += src_w; |
443 | y += src_h; | 444 | y += src_h; |
444 | } | 445 | } |
@@ -546,6 +547,9 @@ ivb_update_plane(struct drm_plane *plane, | |||
546 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | 547 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
547 | sprctl |= SPRITE_TILED; | 548 | sprctl |= SPRITE_TILED; |
548 | 549 | ||
550 | if (rotation & DRM_ROTATE_180) | ||
551 | sprctl |= SPRITE_ROTATE_180; | ||
552 | |||
549 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | 553 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
550 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; | 554 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
551 | else | 555 | else |
@@ -566,14 +570,11 @@ ivb_update_plane(struct drm_plane *plane, | |||
566 | intel_add_fb_offsets(&x, &y, plane_state, 0); | 570 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
567 | sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | 571 | sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); |
568 | 572 | ||
569 | if (rotation & DRM_ROTATE_180) { | 573 | /* HSW+ does this automagically in hardware */ |
570 | sprctl |= SPRITE_ROTATE_180; | 574 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && |
571 | 575 | rotation & DRM_ROTATE_180) { | |
572 | /* HSW and BDW does this automagically in hardware */ | 576 | x += src_w; |
573 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | 577 | y += src_h; |
574 | x += src_w; | ||
575 | y += src_h; | ||
576 | } | ||
577 | } | 578 | } |
578 | 579 | ||
579 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); | 580 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
@@ -684,6 +685,9 @@ ilk_update_plane(struct drm_plane *plane, | |||
684 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | 685 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
685 | dvscntr |= DVS_TILED; | 686 | dvscntr |= DVS_TILED; |
686 | 687 | ||
688 | if (rotation & DRM_ROTATE_180) | ||
689 | dvscntr |= DVS_ROTATE_180; | ||
690 | |||
687 | if (IS_GEN6(dev_priv)) | 691 | if (IS_GEN6(dev_priv)) |
688 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | 692 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
689 | 693 | ||
@@ -701,8 +705,6 @@ ilk_update_plane(struct drm_plane *plane, | |||
701 | dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | 705 | dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); |
702 | 706 | ||
703 | if (rotation & DRM_ROTATE_180) { | 707 | if (rotation & DRM_ROTATE_180) { |
704 | dvscntr |= DVS_ROTATE_180; | ||
705 | |||
706 | x += src_w; | 708 | x += src_w; |
707 | y += src_h; | 709 | y += src_h; |
708 | } | 710 | } |