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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-06 08:55:52 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-06 16:35:44 -0400
commitbb760063790fbbc3c956f23aff4dbdfdd3c03818 (patch)
tree98eb28033453c59d178793c3fb4d37189fd010cd /drivers/gpu/drm/i915/intel_sdvo.c
parenta38911a3fede294e2adfd2deea8104dfbbd760c5 (diff)
drm/i915: pipe config quirk infrastructure plus sdvo mode.flags fix
For various reasons the hw state readout might not be able to faithfully match the hw state: - broken hw (like the case which motivated this patch here where the sdvo encoder does not implemented mandatory functionality correctly). - platforms which are not supported fully with the pipe config infrastructure - if our code doesn't support a given hw configuration natively, e.g. special restrictions on the per-pipe panel fitters when they're used in high-quality scaling modes. In all these cases both fastboot and the hw state cross checker need to be aware of these cases and act accordingly. To be able to do this add a new quirk flag to the pipe config structure. The specific case at hand is an sdvo encoder which doesn't implement the get_timings function, so adjusted_mode flags will be wrong. The strange thing though is that the encoder _does_ work, even though it doesn't implement any of the timings functions (so neither get nor set, neither for input nor output timings). Not that non-compliant sdvo encoder are any surprise at all ... v2: - Don't read random garbage from the dtd if the get_timings call failed (suggested by Chris). - Still check the interlaced flag, that's read out from someplace else. We want maximal paranoia, after all. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo.c')
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 5c816dd75bec..960358d8e336 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1324,19 +1324,21 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
1324 1324
1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1326 if (!ret) { 1326 if (!ret) {
1327 /* Some sdvo encoders are not spec compliant and don't
1328 * implement the mandatory get_timings function. */
1327 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1329 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1328 return; 1330 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1329 } 1331 } else {
1330 1332 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1331 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1333 flags |= DRM_MODE_FLAG_PHSYNC;
1332 flags |= DRM_MODE_FLAG_PHSYNC; 1334 else
1333 else 1335 flags |= DRM_MODE_FLAG_NHSYNC;
1334 flags |= DRM_MODE_FLAG_NHSYNC;
1335 1336
1336 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1337 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1337 flags |= DRM_MODE_FLAG_PVSYNC; 1338 flags |= DRM_MODE_FLAG_PVSYNC;
1338 else 1339 else
1339 flags |= DRM_MODE_FLAG_NVSYNC; 1340 flags |= DRM_MODE_FLAG_NVSYNC;
1341 }
1340 1342
1341 pipe_config->adjusted_mode.flags |= flags; 1343 pipe_config->adjusted_mode.flags |= flags;
1342 1344