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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-10-06 12:22:21 -0400
committerAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-10-28 05:25:03 -0400
commite7583f7b1018a862b2c93fd50650181881b2a0e1 (patch)
tree658c788dd202658baa3471c42c5f72c71d68a519 /drivers/gpu/drm/i915/intel_runtime_pm.c
parent842d416654ebbcae86c32c0a354da9f649335410 (diff)
drm/i915: Add location of the Rcomp resistor to bxt_ddi_phy_info
Use struct bxt_ddi_phy_info to hold information of where the Rcomp resistor is located, instead of hard coding it in the init sequence. Note that this moves the enabling of the phy with the Rcomp resistor out of the power well enable code. That should be safe since bxt_ddi_phy_init() is called while the power domains lock is held, and that is the only way that function gets called, so there is no possibility of a concurrent phy enable caused by a power domain get call. v2: Replace comment about lock with lockdep_assert_held() (Imre) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/62d209950ad48484564f3e793cf247cf62572a39.1475770848.git-series.ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5fd76ee0f4ca..95034a06d4ad 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -848,22 +848,7 @@ static void skl_power_well_disable(struct drm_i915_private *dev_priv,
848static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 848static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
849 struct i915_power_well *power_well) 849 struct i915_power_well *power_well)
850{ 850{
851 enum skl_disp_power_wells power_well_id = power_well->id;
852 struct i915_power_well *cmn_a_well = NULL;
853
854 if (power_well_id == BXT_DPIO_CMN_BC) {
855 /*
856 * We need to copy the GRC calibration value from the eDP PHY,
857 * so make sure it's powered up.
858 */
859 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
860 intel_power_well_get(dev_priv, cmn_a_well);
861 }
862
863 bxt_ddi_phy_init(dev_priv, power_well->data); 851 bxt_ddi_phy_init(dev_priv, power_well->data);
864
865 if (cmn_a_well)
866 intel_power_well_put(dev_priv, cmn_a_well);
867} 852}
868 853
869static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 854static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,