drm/i915/icl: Enable 2nd DBuf slice only when needed

ICL has two slices of DBuf, each slice of size 1024 blocks.
We should not always enable slice-2. It should be enabled only if
display total required BW is > 12GBps OR more than 1 pipes are enabled.

Changes since V1:
 - typecast total_data_rate to u64 before multiplication to solve any
   possible overflow (Rodrigo)
 - fix where skl_wm_get_hw_state was memsetting ddb, resulting
   enabled_slices to become zero
 - Fix the logic of calculating ddb_size
Changes since V2:
 - If no-crtc is part of commit required_slices will have value "0",
   don't try to disable DBuf slice.
Changes since V3:
 - Create a generic helper to enable/disable slice
 - don't return early if total_data_rate is 0, it may be cursor only
   commit, or atomic modeset without any plane.
Changes since V4:
 - Solve checkpatch warnings
 - use kernel types u8/u64 instead of uint8_t/uint64_t
Changes since V5:
 - Rebase

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-3-mahesh1.kumar@intel.com

1 files changed, 51 insertions, 14 deletions

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index afc6ef81ca0c..3fffbfe4521d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2619,32 +2619,69 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
         mutex_unlock(&power_domains->lock);
 }
 
-static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
+static inline
+bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv,
+                          i915_reg_t reg, bool enable)
 {
-        I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
-        POSTING_READ(DBUF_CTL);
+        u32 val, status;
 
+        val = I915_READ(reg);
+        val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST);
+        I915_WRITE(reg, val);
+        POSTING_READ(reg);
         udelay(10);
 
-        if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
-                DRM_ERROR("DBuf power enable timeout\n");
+        status = I915_READ(reg) & DBUF_POWER_STATE;
+        if ((enable && !status) || (!enable && status)) {
+                DRM_ERROR("DBus power %s timeout!\n",
+                          enable ? "enable" : "disable");
+                return false;
+        }
+        return true;
+}
+
+static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+        intel_dbuf_slice_set(dev_priv, DBUF_CTL, true);
 }
 
 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 {
-        I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
-        POSTING_READ(DBUF_CTL);
+        intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
+}
 
-        udelay(10);
+static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+{
+        if (INTEL_GEN(dev_priv) < 11)
+                return 1;
+        return 2;
+}
 
-        if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-                DRM_ERROR("DBuf power disable timeout!\n");
+void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
+                            u8 req_slices)
+{
+        u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+        u32 val;
+        bool ret;
+
+        if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+                DRM_ERROR("Invalid number of dbuf slices requested\n");
+                return;
+        }
+
+        if (req_slices == hw_enabled_slices || req_slices == 0)
+                return;
+
+        val = I915_READ(DBUF_CTL_S2);
+        if (req_slices > hw_enabled_slices)
+                ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
+        else
+                ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+
+        if (ret)
+                dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
 }
 
-/*
- * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it when
- * needed and keep it disabled as much as possible.
- */
 static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
 {
         I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);