drm/i915/cnl: Add AUX-F support

On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.

There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.

v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Rebase and fix commit message.
v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
v6: Rebase on top of display headers rework.
v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
v8: Fix Aux bits for Port F (DK)
v9: Fix VBT definition of Port F (DK).
v10: Squash power well addition to this patch to avoid
     warns as pointed by DK.
v11: Clean up squashed commit message. (David)
v12: Remove unnecessary handling for older platforms (DK)
     Adding AUX_F to PG2 following other existent ones. (DK)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-2-rodrigo.vivi@intel.com

1 files changed, 22 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5b1aa4b9c72c..a274e930f045 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -124,6 +124,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
                 return "AUX_C";
         case POWER_DOMAIN_AUX_D:
                 return "AUX_D";
+        case POWER_DOMAIN_AUX_F:
+                return "AUX_F";
         case POWER_DOMAIN_GMBUS:
                 return "GMBUS";
         case POWER_DOMAIN_INIT:
@@ -1828,6 +1830,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT_ULL(POWER_DOMAIN_AUX_B) |                       \
         BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
         BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
         BIT_ULL(POWER_DOMAIN_VGA) |                             \
         BIT_ULL(POWER_DOMAIN_INIT))
@@ -1855,6 +1858,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 #define CNL_DISPLAY_AUX_D_POWER_DOMAINS (               \
         BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
         BIT_ULL(POWER_DOMAIN_INIT))
+#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (               \
+        BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
+        BIT_ULL(POWER_DOMAIN_INIT))
 #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
         CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
         BIT_ULL(POWER_DOMAIN_GT_IRQ) |                  \
@@ -2405,6 +2411,12 @@ static struct i915_power_well cnl_power_wells[] = {
                 .ops = &hsw_power_well_ops,
                 .id = SKL_DISP_PW_DDI_D,
         },
+        {
+                .name = "AUX F",
+                .domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = CNL_DISP_PW_AUX_F,
+        },
 };
 
 static int
@@ -2520,6 +2532,16 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
                 set_power_wells(power_domains, skl_power_wells);
         } else if (IS_CANNONLAKE(dev_priv)) {
                 set_power_wells(power_domains, cnl_power_wells);
+
+                /*
+                 * Aux IO is getting enabled for all ports
+                 * regardless the presence or use. So, in order to avoid
+                 * timeouts, lets remove it from the list
+                 * for the SKUs without port F.
+                 */
+                if (!IS_CNL_WITH_PORT_F(dev_priv))
+                        power_domains->power_well_count -= 1;
+
         } else if (IS_BROXTON(dev_priv)) {
                 set_power_wells(power_domains, bxt_power_wells);
         } else if (IS_GEMINILAKE(dev_priv)) {