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authorVille Syrjälä <ville.syrjala@linux.intel.com>2016-04-18 07:02:28 -0400
committerVille Syrjälä <ville.syrjala@linux.intel.com>2016-04-19 07:43:22 -0400
commit9d0996b5903fec7bff64e169b860146a923a6abe (patch)
tree16a4b6a2cfda9d021052c522d815a745e1f9812b /drivers/gpu/drm/i915/intel_runtime_pm.c
parent465ac0c6b619843f72e36c280cdfa6abf79b7a09 (diff)
drm/i915: Define HSW/BDW display power domains the right way up
Currently we're trying to define HSW/BDW power wells by what's not included. Let's do it the other way around, so that you can actually tell when the power well would get enabled. This will also allow us to add new power domains without accidentally adding it to the HSW/BDW display power domains. The current set of domains looks rather buggy even: - POWER_DOMAIN_MODESET is included in the display power well needlessly - DDI-B to DDI-E were not part of the display power well when they should be So let's fix that up while at it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460977348-32260-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c45
1 files changed, 26 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index aae8545d75df..06d14c4904a3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1592,30 +1592,37 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
1592 intel_runtime_pm_put(dev_priv); 1592 intel_runtime_pm_put(dev_priv);
1593} 1593}
1594 1594
1595#define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1595#define HSW_DISPLAY_POWER_DOMAINS ( \
1596 BIT(POWER_DOMAIN_PIPE_A) | \ 1596 BIT(POWER_DOMAIN_PIPE_B) | \
1597 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1597 BIT(POWER_DOMAIN_PIPE_C) | \
1598 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1598 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1599 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1600 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1601 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1602 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1603 BIT(POWER_DOMAIN_TRANSCODER_C) | \
1599 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1604 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1600 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1605 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1601 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1606 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1602 BIT(POWER_DOMAIN_PORT_CRT) | \ 1607 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1603 BIT(POWER_DOMAIN_PLLS) | \ 1608 BIT(POWER_DOMAIN_VGA) | \
1604 BIT(POWER_DOMAIN_AUX_A) | \ 1609 BIT(POWER_DOMAIN_AUDIO) | \
1605 BIT(POWER_DOMAIN_AUX_B) | \
1606 BIT(POWER_DOMAIN_AUX_C) | \
1607 BIT(POWER_DOMAIN_AUX_D) | \
1608 BIT(POWER_DOMAIN_GMBUS) | \
1609 BIT(POWER_DOMAIN_INIT))
1610#define HSW_DISPLAY_POWER_DOMAINS ( \
1611 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1612 BIT(POWER_DOMAIN_INIT)) 1610 BIT(POWER_DOMAIN_INIT))
1613 1611
1614#define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1612#define BDW_DISPLAY_POWER_DOMAINS ( \
1615 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1613 BIT(POWER_DOMAIN_PIPE_B) | \
1616 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1614 BIT(POWER_DOMAIN_PIPE_C) | \
1617#define BDW_DISPLAY_POWER_DOMAINS ( \ 1615 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1618 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1616 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1617 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1618 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1619 BIT(POWER_DOMAIN_TRANSCODER_C) | \
1620 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1621 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1622 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1623 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1624 BIT(POWER_DOMAIN_VGA) | \
1625 BIT(POWER_DOMAIN_AUDIO) | \
1619 BIT(POWER_DOMAIN_INIT)) 1626 BIT(POWER_DOMAIN_INIT))
1620 1627
1621#define VLV_DISPLAY_POWER_DOMAINS ( \ 1628#define VLV_DISPLAY_POWER_DOMAINS ( \