Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Higlights here goes to many PSR fixes and improvements; to the Ice lake work with
power well support and begin of DSI support addition. Also there were many improvements
on execlists and interrupts for minimal latency on command submission; and many fixes
on selftests, mostly caught by our CI.

General driver:
- Clean-up on aux irq (Lucas)
- Mark expected switch fall-through for dealing with static analysis tools (Gustavo)

Gem:
- Different fixes for GuC (Chris, Anusha, Michal)
- Avoid self-relocation BIAS if no relocation (Chris)
- Improve debugging cases in on EINVAL return and vma allocation (Chris)
- Fixes and improvements on context destroying and freeing (Chris)
- Wait for engines to idle before retiring (Chris)
- Many improvements on execlists and interrupts for minimal latency on command submission (Chris)
- Many fixes in selftests, specially on cases highlighted on CI (Chris)
- Other fixes and improvements around GGTT (Chris)
- Prevent background reaping of active objects (Chris)

Display:
- Parallel modeset cleanup to fix driver reset (Chris)
- Get AUX power domain for DP main link (Imre)
- Clean-up on PSR unused func pointers (Rodrigo)
- Many PSR/PSR2 fixes and improvements (DK, Jose, Tarun)
- Add a PSR1 live status (Vathsala)
- Replace old drm_*_{un/reference} with put,get functions (Thomas)
- FBC fixes (Maarten)
- Abstract and document the usage of picking macros (Jani)
- Remove unnecessary check for unsupported modifiers for NV12. (DK)
- Interrupt fixes for display (Ville)
- Clean up on sdvo code (Ville)
- Clean up on current DSI code (Jani)
- Remove support for legacy debugfs crc interface (Maarten)
- Simplify get_encoder_power_domains (Imre)

Icelake:
- MG PLL fixes (Imre)
- Add hw workaround for alpha blending (Vandita)
- Add power well support (Imre)
- Add Interrupt Support (Anusha)
- Start to add support for DSI on Ice Lake (Madhav)

Signed-off-by: Dave Airlie <airlied@redhat.com>

# gpg: Signature made Tue 10 Jul 2018 08:41:37 AM AEST
# gpg:                using RSA key FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>"
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA
Link: https://patchwork.freedesktop.org/patch/msgid/20180710234349.GA16562@intel.com

1 files changed, 324 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index de3a81034f77..6b5aa3b074ec 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -134,6 +134,14 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
                 return "AUX_F";
         case POWER_DOMAIN_AUX_IO_A:
                 return "AUX_IO_A";
+        case POWER_DOMAIN_AUX_TBT1:
+                return "AUX_TBT1";
+        case POWER_DOMAIN_AUX_TBT2:
+                return "AUX_TBT2";
+        case POWER_DOMAIN_AUX_TBT3:
+                return "AUX_TBT3";
+        case POWER_DOMAIN_AUX_TBT4:
+                return "AUX_TBT4";
         case POWER_DOMAIN_GMBUS:
                 return "GMBUS";
         case POWER_DOMAIN_INIT:
@@ -384,7 +392,8 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
         u32 val;
 
         if (wait_fuses) {
-                pg = SKL_PW_TO_PG(id);
+                pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_TO_PG(id) :
+                                                 SKL_PW_TO_PG(id);
                 /*
                  * For PW1 we have to wait both for the PW0/PG0 fuse state
                  * before enabling the power well and PW1/PG1's own fuse
@@ -430,6 +439,43 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
         hsw_wait_for_power_well_disable(dev_priv, power_well);
 }
 
+#define ICL_AUX_PW_TO_PORT(pw)  ((pw) - ICL_DISP_PW_AUX_A)
+
+static void
+icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+                                    struct i915_power_well *power_well)
+{
+        enum i915_power_well_id id = power_well->id;
+        enum port port = ICL_AUX_PW_TO_PORT(id);
+        u32 val;
+
+        val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
+        I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
+
+        val = I915_READ(ICL_PORT_CL_DW12(port));
+        I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+
+        hsw_wait_for_power_well_enable(dev_priv, power_well);
+}
+
+static void
+icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
+                                     struct i915_power_well *power_well)
+{
+        enum i915_power_well_id id = power_well->id;
+        enum port port = ICL_AUX_PW_TO_PORT(id);
+        u32 val;
+
+        val = I915_READ(ICL_PORT_CL_DW12(port));
+        I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+
+        val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));
+        I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id),
+                   val & ~HSW_PWR_WELL_CTL_REQ(id));
+
+        hsw_wait_for_power_well_disable(dev_priv, power_well);
+}
+
 /*
  * We should only use the power well if we explicitly asked the hardware to
  * enable it, so check if it's enabled and also check if we've requested it to
@@ -1824,6 +1870,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT_ULL(POWER_DOMAIN_INIT))
 #define GLK_DISPLAY_AUX_A_POWER_DOMAINS (               \
         BIT_ULL(POWER_DOMAIN_AUX_A) |           \
+        BIT_ULL(POWER_DOMAIN_AUX_IO_A) |                \
         BIT_ULL(POWER_DOMAIN_INIT))
 #define GLK_DISPLAY_AUX_B_POWER_DOMAINS (               \
         BIT_ULL(POWER_DOMAIN_AUX_B) |           \
@@ -1896,6 +1943,105 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
         BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
         BIT_ULL(POWER_DOMAIN_INIT))
 
+/*
+ * ICL PW_0/PG_0 domains (HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - central power except FBC
+ * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
+ * ICL PW_1/PG_1 domains (HW/DMC control):
+ * - DBUF function
+ * - PIPE_A and its planes, except VGA
+ * - transcoder EDP + PSR
+ * - transcoder DSI
+ * - DDI_A
+ * - FBC
+ */
+#define ICL_PW_4_POWER_DOMAINS (                        \
+        BIT_ULL(POWER_DOMAIN_PIPE_C) |                  \
+        BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |     \
+        BIT_ULL(POWER_DOMAIN_INIT))
+        /* VDSC/joining */
+#define ICL_PW_3_POWER_DOMAINS (                        \
+        ICL_PW_4_POWER_DOMAINS |                        \
+        BIT_ULL(POWER_DOMAIN_PIPE_B) |                  \
+        BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |            \
+        BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |            \
+        BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |            \
+        BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |        \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) |           \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |        \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) |           \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |        \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) |           \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |        \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) |           \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |        \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) |           \
+        BIT_ULL(POWER_DOMAIN_AUX_B) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_C) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_D) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_E) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_F) |                   \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT1) |                \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT2) |                \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT3) |                \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT4) |                \
+        BIT_ULL(POWER_DOMAIN_VGA) |                     \
+        BIT_ULL(POWER_DOMAIN_AUDIO) |                   \
+        BIT_ULL(POWER_DOMAIN_INIT))
+        /*
+         * - transcoder WD
+         * - KVMR (HW control)
+         */
+#define ICL_PW_2_POWER_DOMAINS (                        \
+        ICL_PW_3_POWER_DOMAINS |                        \
+        BIT_ULL(POWER_DOMAIN_INIT))
+        /*
+         * - eDP/DSI VDSC
+         * - KVMR (HW control)
+         */
+#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
+        ICL_PW_2_POWER_DOMAINS |                        \
+        BIT_ULL(POWER_DOMAIN_MODESET) |                 \
+        BIT_ULL(POWER_DOMAIN_AUX_A) |                   \
+        BIT_ULL(POWER_DOMAIN_INIT))
+
+#define ICL_DDI_IO_A_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
+#define ICL_DDI_IO_B_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
+#define ICL_DDI_IO_C_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
+#define ICL_DDI_IO_D_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
+#define ICL_DDI_IO_E_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
+#define ICL_DDI_IO_F_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
+
+#define ICL_AUX_A_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_A))
+#define ICL_AUX_B_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_B))
+#define ICL_AUX_C_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_C))
+#define ICL_AUX_D_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_D))
+#define ICL_AUX_E_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_E))
+#define ICL_AUX_F_IO_POWER_DOMAINS (                    \
+        BIT_ULL(POWER_DOMAIN_AUX_F))
+#define ICL_AUX_TBT1_IO_POWER_DOMAINS (                 \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT1))
+#define ICL_AUX_TBT2_IO_POWER_DOMAINS (                 \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT2))
+#define ICL_AUX_TBT3_IO_POWER_DOMAINS (                 \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT3))
+#define ICL_AUX_TBT4_IO_POWER_DOMAINS (                 \
+        BIT_ULL(POWER_DOMAIN_AUX_TBT4))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
         .sync_hw = i9xx_power_well_sync_hw_noop,
         .enable = i9xx_always_on_power_well_noop,
@@ -2453,6 +2599,157 @@ static struct i915_power_well cnl_power_wells[] = {
         },
 };
 
+static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = {
+        .sync_hw = hsw_power_well_sync_hw,
+        .enable = icl_combo_phy_aux_power_well_enable,
+        .disable = icl_combo_phy_aux_power_well_disable,
+        .is_enabled = hsw_power_well_enabled,
+};
+
+static struct i915_power_well icl_power_wells[] = {
+        {
+                .name = "always-on",
+                .always_on = 1,
+                .domains = POWER_DOMAIN_MASK,
+                .ops = &i9xx_always_on_power_well_ops,
+                .id = I915_DISP_PW_ALWAYS_ON,
+        },
+        {
+                .name = "power well 1",
+                /* Handled by the DMC firmware */
+                .domains = 0,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_1,
+                .hsw.has_fuses = true,
+        },
+        {
+                .name = "power well 2",
+                .domains = ICL_PW_2_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_2,
+                .hsw.has_fuses = true,
+        },
+        {
+                .name = "DC off",
+                .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+                .ops = &gen9_dc_off_power_well_ops,
+                .id = SKL_DISP_PW_DC_OFF,
+        },
+        {
+                .name = "power well 3",
+                .domains = ICL_PW_3_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_3,
+                .hsw.irq_pipe_mask = BIT(PIPE_B),
+                .hsw.has_vga = true,
+                .hsw.has_fuses = true,
+        },
+        {
+                .name = "DDI A IO",
+                .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_A,
+        },
+        {
+                .name = "DDI B IO",
+                .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_B,
+        },
+        {
+                .name = "DDI C IO",
+                .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_C,
+        },
+        {
+                .name = "DDI D IO",
+                .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_D,
+        },
+        {
+                .name = "DDI E IO",
+                .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_E,
+        },
+        {
+                .name = "DDI F IO",
+                .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_DDI_F,
+        },
+        {
+                .name = "AUX A",
+                .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+                .ops = &icl_combo_phy_aux_power_well_ops,
+                .id = ICL_DISP_PW_AUX_A,
+        },
+        {
+                .name = "AUX B",
+                .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+                .ops = &icl_combo_phy_aux_power_well_ops,
+                .id = ICL_DISP_PW_AUX_B,
+        },
+        {
+                .name = "AUX C",
+                .domains = ICL_AUX_C_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_C,
+        },
+        {
+                .name = "AUX D",
+                .domains = ICL_AUX_D_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_D,
+        },
+        {
+                .name = "AUX E",
+                .domains = ICL_AUX_E_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_E,
+        },
+        {
+                .name = "AUX F",
+                .domains = ICL_AUX_F_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_F,
+        },
+        {
+                .name = "AUX TBT1",
+                .domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_TBT1,
+        },
+        {
+                .name = "AUX TBT2",
+                .domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_TBT2,
+        },
+        {
+                .name = "AUX TBT3",
+                .domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_TBT3,
+        },
+        {
+                .name = "AUX TBT4",
+                .domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_AUX_TBT4,
+        },
+        {
+                .name = "power well 4",
+                .domains = ICL_PW_4_POWER_DOMAINS,
+                .ops = &hsw_power_well_ops,
+                .id = ICL_DISP_PW_4,
+                .hsw.has_fuses = true,
+                .hsw.irq_pipe_mask = BIT(PIPE_C),
+        },
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
                                    int disable_power_well)
@@ -2470,7 +2767,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
         int requested_dc;
         int max_dc;
 
-        if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+        if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) {
                 max_dc = 2;
                 mask = 0;
         } else if (IS_GEN9_LP(dev_priv)) {
@@ -2558,7 +2855,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
          * The enabling order will be from lower to higher indexed wells,
          * the disabling order is reversed.
          */
-        if (IS_HASWELL(dev_priv)) {
+        if (IS_ICELAKE(dev_priv)) {
+                set_power_wells(power_domains, icl_power_wells);
+        } else if (IS_HASWELL(dev_priv)) {
                 set_power_wells(power_domains, hsw_power_wells);
         } else if (IS_BROADWELL(dev_priv)) {
                 set_power_wells(power_domains, bdw_power_wells);
@@ -2913,6 +3212,7 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
         switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
         default:
                 MISSING_CASE(val);
+                /* fall through */
         case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
                 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
                 break;
@@ -3025,6 +3325,8 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 static void icl_display_core_init(struct drm_i915_private *dev_priv,
                                   bool resume)
 {
+        struct i915_power_domains *power_domains = &dev_priv->power_domains;
+        struct i915_power_well *well;
         enum port port;
         u32 val;
 
@@ -3053,8 +3355,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
                 I915_WRITE(ICL_PORT_CL_DW5(port), val);
         }
 
-        /* 4. Enable power well 1 (PG1) and aux IO power. */
-        /* FIXME: ICL power wells code not here yet. */
+        /*
+         * 4. Enable Power Well 1 (PG1).
+         *    The AUX IO power wells will be enabled on demand.
+         */
+        mutex_lock(&power_domains->lock);
+        well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
+        intel_power_well_enable(dev_priv, well);
+        mutex_unlock(&power_domains->lock);
 
         /* 5. Enable CDCLK. */
         icl_init_cdclk(dev_priv);
@@ -3072,6 +3380,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 
 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 {
+        struct i915_power_domains *power_domains = &dev_priv->power_domains;
+        struct i915_power_well *well;
         enum port port;
         u32 val;
 
@@ -3085,8 +3395,15 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
         /* 3. Disable CD clock */
         icl_uninit_cdclk(dev_priv);
 
-        /* 4. Disable Power Well 1 (PG1) and Aux IO Power */
-        /* FIXME: ICL power wells code not here yet. */
+        /*
+         * 4. Disable Power Well 1 (PG1).
+         *    The AUX IO power wells are toggled on demand, so they are already
+         *    disabled at this point.
+         */
+        mutex_lock(&power_domains->lock);
+        well = lookup_power_well(dev_priv, ICL_DISP_PW_1);
+        intel_power_well_disable(dev_priv, well);
+        mutex_unlock(&power_domains->lock);
 
         /* 5. Disable Comp */
         for (port = PORT_A; port <= PORT_B; port++) {