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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2018-09-16 06:53:30 -0400 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-09-26 09:01:52 -0400 |
| commit | 35c37ade79cdfe731ca1cae50c6628fef98a69a5 (patch) | |
| tree | 2f9625f5b060f915ae83b304cdc67914837ff487 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | 33868a91c1d9627b5003b8e299c46c6cfee4ff18 (diff) | |
drm/i915/icl: Define TA_TIMING_PARAM registers
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
v2: Changes (Jani N)
- Define mask/shift for bitfields
- Use bitfields name as per BSPEC
- Define remaining bitfields
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-8-git-send-email-madhav.chauhan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
0 files changed, 0 insertions, 0 deletions