drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

In Indirect context w/a batch buffer,
+WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

v2: SKL revision id was used for BXT, copy paste error found during
internal review (Bob Beckett).

v3: explain why part of the WA is in Per ctx batch (Mika)

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 5 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bddc9032e17e..1c14233d179f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -946,8 +946,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
                 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
-                WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
-                                  DISABLE_PIXEL_MASK_CAMMING);
+                /*
+                 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
+                 * but we do that in per ctx batchbuffer as there is an issue
+                 * with this register not getting restored on ctx restore
+                 */
         }
 
         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||