drm/i915: Limit FBC flush to post batch flush

Don't issue the FBC nuke/cache clean command when invalidate_domains!=0.
That would indicate that we're not being called for the post-batch
flush.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c2f09d456300..e26e18a1d916 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -354,7 +354,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
         intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
-        if (flush_domains)
+        if (!invalidate_domains && flush_domains)
                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 
         return 0;
@@ -1838,7 +1838,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
         }
         intel_ring_advance(ring);
 
-        if (IS_GEN7(dev) && flush)
+        if (IS_GEN7(dev) && !invalidate && flush)
                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
 
         return 0;