diff options
author | Kenneth Graunke <kenneth@whitecape.org> | 2014-06-27 19:04:20 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-07 08:01:12 -0400 |
commit | 884ceacee308f0e4616d0c933518af2639f7b1d8 (patch) | |
tree | 2987be5d1b84d2793b1e3b6d0692b3018490ed86 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
parent | 69bbeb4ae7b05c094b593b5df4f7a68f713589be (diff) |
drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
We'll want to reuse this for a workaround.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Rmove now unused int.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b3d8f766fa7f..2908896334f5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -380,12 +380,32 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, | |||
380 | } | 380 | } |
381 | 381 | ||
382 | static int | 382 | static int |
383 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | ||
384 | u32 flags, u32 scratch_addr) | ||
385 | { | ||
386 | int ret; | ||
387 | |||
388 | ret = intel_ring_begin(ring, 6); | ||
389 | if (ret) | ||
390 | return ret; | ||
391 | |||
392 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | ||
393 | intel_ring_emit(ring, flags); | ||
394 | intel_ring_emit(ring, scratch_addr); | ||
395 | intel_ring_emit(ring, 0); | ||
396 | intel_ring_emit(ring, 0); | ||
397 | intel_ring_emit(ring, 0); | ||
398 | intel_ring_advance(ring); | ||
399 | |||
400 | return 0; | ||
401 | } | ||
402 | |||
403 | static int | ||
383 | gen8_render_ring_flush(struct intel_engine_cs *ring, | 404 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
384 | u32 invalidate_domains, u32 flush_domains) | 405 | u32 invalidate_domains, u32 flush_domains) |
385 | { | 406 | { |
386 | u32 flags = 0; | 407 | u32 flags = 0; |
387 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | 408 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
388 | int ret; | ||
389 | 409 | ||
390 | flags |= PIPE_CONTROL_CS_STALL; | 410 | flags |= PIPE_CONTROL_CS_STALL; |
391 | 411 | ||
@@ -404,20 +424,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, | |||
404 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | 424 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
405 | } | 425 | } |
406 | 426 | ||
407 | ret = intel_ring_begin(ring, 6); | 427 | return gen8_emit_pipe_control(ring, flags, scratch_addr); |
408 | if (ret) | ||
409 | return ret; | ||
410 | |||
411 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | ||
412 | intel_ring_emit(ring, flags); | ||
413 | intel_ring_emit(ring, scratch_addr); | ||
414 | intel_ring_emit(ring, 0); | ||
415 | intel_ring_emit(ring, 0); | ||
416 | intel_ring_emit(ring, 0); | ||
417 | intel_ring_advance(ring); | ||
418 | |||
419 | return 0; | ||
420 | |||
421 | } | 428 | } |
422 | 429 | ||
423 | static void ring_write_tail(struct intel_engine_cs *ring, | 430 | static void ring_write_tail(struct intel_engine_cs *ring, |