drm/i915: Remove obsolete ringbuffer emission for gen8+

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks
(bdw i7-5557u, 20170324):
                                        ring          execlists
exec continuous nops on all rings:   1.491us            2.223us
exec sequential nops on each ring:  12.508us           53.682us
single nop + sync:                   9.272us           30.291us

vblank_mode=0 glxgears:            ~11000fps           ~9000fps

Since the earlier submission, gen8 ringbuffer submission has fallen
further and further behind in features. So while ringbuffer may hold the
throughput crown, in terms of interactive latency, execlists is much
better. Alas, we have no convenient metrics for such, other than
demonstrating things we can do with execlists but can not using
legacy ringbuffer submission.

We have made a few improvements to lowlevel execlists throughput,
and ringbuffer currently panics on boot! (bdw i7-5557u, 20171026):

                                        ring          execlists
exec continuous nops on all rings:       n/a            1.921us
exec sequential nops on each ring:       n/a           44.621us
single nop + sync:                       n/a           21.953us

vblank_mode=0 glxgears:                  n/a          ~18500fps

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Once-upon-a-time-Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171120205504.21892-2-chris@chris-wilson.co.uk

1 files changed, 63 insertions, 368 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index be98868115bf..5465e708545f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -340,50 +340,6 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
         return 0;
 }
 
-static int
-gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
-{
-        u32 flags;
-        u32 *cs;
-
-        cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6);
-        if (IS_ERR(cs))
-                return PTR_ERR(cs);
-
-        flags = PIPE_CONTROL_CS_STALL;
-
-        if (mode & EMIT_FLUSH) {
-                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
-                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
-                flags |= PIPE_CONTROL_FLUSH_ENABLE;
-        }
-        if (mode & EMIT_INVALIDATE) {
-                flags |= PIPE_CONTROL_TLB_INVALIDATE;
-                flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
-                flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-                flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
-                flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
-                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-                flags |= PIPE_CONTROL_QW_WRITE;
-                flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
-
-                /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
-                cs = gen8_emit_pipe_control(cs,
-                                            PIPE_CONTROL_CS_STALL |
-                                            PIPE_CONTROL_STALL_AT_SCOREBOARD,
-                                            0);
-        }
-
-        cs = gen8_emit_pipe_control(cs, flags,
-                                    i915_ggtt_offset(req->engine->scratch) +
-                                    2 * CACHELINE_BYTES);
-
-        intel_ring_advance(req, cs);
-
-        return 0;
-}
-
 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 {
         struct drm_i915_private *dev_priv = engine->i915;
@@ -427,7 +383,6 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
         } else if (IS_GEN6(dev_priv)) {
                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
         } else {
-                /* XXX: gen8 returns to sanity */
                 mmio = RING_HWS_PGA(engine->mmio_base);
         }
 
@@ -437,13 +392,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
         I915_WRITE(mmio, engine->status_page.ggtt_offset);
         POSTING_READ(mmio);
 
-        /*
-         * Flush the TLB for this page
-         *
-         * FIXME: These two bits have disappeared on gen8, so a question
-         * arises: do we still need this and if so how should we go about
-         * invalidating the TLB?
-         */
+        /* Flush the TLB for this page */
         if (IS_GEN(dev_priv, 6, 7)) {
                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 
@@ -611,8 +560,6 @@ static void reset_ring_common(struct intel_engine_cs *engine,
                 struct intel_context *ce = &request->ctx->engine[engine->id];
                 struct i915_hw_ppgtt *ppgtt;
 
-                /* FIXME consider gen8 reset */
-
                 if (ce->state) {
                         I915_WRITE(CCID,
                                    i915_ggtt_offset(ce->state) |
@@ -713,62 +660,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
         return init_workarounds_ring(engine);
 }
 
-static void render_ring_cleanup(struct intel_engine_cs *engine)
-{
-        struct drm_i915_private *dev_priv = engine->i915;
-
-        i915_vma_unpin_and_release(&dev_priv->semaphore);
-}
-
-static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs)
-{
-        struct drm_i915_private *dev_priv = req->i915;
-        struct intel_engine_cs *waiter;
-        enum intel_engine_id id;
-
-        for_each_engine(waiter, dev_priv, id) {
-                u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
-                if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
-                        continue;
-
-                *cs++ = GFX_OP_PIPE_CONTROL(6);
-                *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE |
-                        PIPE_CONTROL_CS_STALL;
-                *cs++ = lower_32_bits(gtt_offset);
-                *cs++ = upper_32_bits(gtt_offset);
-                *cs++ = req->global_seqno;
-                *cs++ = 0;
-                *cs++ = MI_SEMAPHORE_SIGNAL |
-                        MI_SEMAPHORE_TARGET(waiter->hw_id);
-                *cs++ = 0;
-        }
-
-        return cs;
-}
-
-static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs)
-{
-        struct drm_i915_private *dev_priv = req->i915;
-        struct intel_engine_cs *waiter;
-        enum intel_engine_id id;
-
-        for_each_engine(waiter, dev_priv, id) {
-                u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
-                if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
-                        continue;
-
-                *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
-                *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT;
-                *cs++ = upper_32_bits(gtt_offset);
-                *cs++ = req->global_seqno;
-                *cs++ = MI_SEMAPHORE_SIGNAL |
-                        MI_SEMAPHORE_TARGET(waiter->hw_id);
-                *cs++ = 0;
-        }
-
-        return cs;
-}
-
 static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs)
 {
         struct drm_i915_private *dev_priv = req->i915;
@@ -851,70 +742,6 @@ static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
                                     req->engine->semaphore.signal(req, cs));
 }
 
-static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
-                                        u32 *cs)
-{
-        struct intel_engine_cs *engine = req->engine;
-
-        if (engine->semaphore.signal)
-                cs = engine->semaphore.signal(req, cs);
-
-        *cs++ = GFX_OP_PIPE_CONTROL(6);
-        *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
-                PIPE_CONTROL_QW_WRITE;
-        *cs++ = intel_hws_seqno_address(engine);
-        *cs++ = 0;
-        *cs++ = req->global_seqno;
-        /* We're thrashing one dword of HWS. */
-        *cs++ = 0;
-        *cs++ = MI_USER_INTERRUPT;
-        *cs++ = MI_NOOP;
-
-        req->tail = intel_ring_offset(req, cs);
-        assert_ring_tail_valid(req->ring, req->tail);
-}
-
-static const int gen8_render_emit_breadcrumb_sz = 8;
-
-/**
- * intel_ring_sync - sync the waiter to the signaller on seqno
- *
- * @waiter - ring that is waiting
- * @signaller - ring which has, or will signal
- * @seqno - seqno which the waiter will block on
- */
-
-static int
-gen8_ring_sync_to(struct drm_i915_gem_request *req,
-                  struct drm_i915_gem_request *signal)
-{
-        struct drm_i915_private *dev_priv = req->i915;
-        u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
-        struct i915_hw_ppgtt *ppgtt;
-        u32 *cs;
-
-        cs = intel_ring_begin(req, 4);
-        if (IS_ERR(cs))
-                return PTR_ERR(cs);
-
-        *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT |
-                MI_SEMAPHORE_SAD_GTE_SDD;
-        *cs++ = signal->global_seqno;
-        *cs++ = lower_32_bits(offset);
-        *cs++ = upper_32_bits(offset);
-        intel_ring_advance(req, cs);
-
-        /* When the !RCS engines idle waiting upon a semaphore, they lose their
-         * pagetables and we must reload them before executing the batch.
-         * We do this on the i915_switch_context() following the wait and
-         * before the dispatch.
-         */
-        ppgtt = req->ctx->ppgtt;
-        if (ppgtt && req->engine->id != RCS)
-                ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
-        return 0;
-}
-
 static int
 gen6_ring_sync_to(struct drm_i915_gem_request *req,
                   struct drm_i915_gem_request *signal)
@@ -1090,25 +917,6 @@ hsw_vebox_irq_disable(struct intel_engine_cs *engine)
         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 }
 
-static void
-gen8_irq_enable(struct intel_engine_cs *engine)
-{
-        struct drm_i915_private *dev_priv = engine->i915;
-
-        I915_WRITE_IMR(engine,
-                       ~(engine->irq_enable_mask |
-                         engine->irq_keep_mask));
-        POSTING_READ_FW(RING_IMR(engine->mmio_base));
-}
-
-static void
-gen8_irq_disable(struct intel_engine_cs *engine)
-{
-        struct drm_i915_private *dev_priv = engine->i915;
-
-        I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
-}
-
 static int
 i965_emit_bb_start(struct drm_i915_gem_request *req,
                    u64 offset, u32 length,
@@ -1796,8 +1604,6 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
                 return PTR_ERR(cs);
 
         cmd = MI_FLUSH_DW;
-        if (INTEL_GEN(req->i915) >= 8)
-                cmd += 1;
 
         /* We always require a command barrier so that subsequent
          * commands, such as breadcrumb interrupts, are strictly ordered
@@ -1817,38 +1623,9 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 
         *cs++ = cmd;
         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
-        if (INTEL_GEN(req->i915) >= 8) {
-                *cs++ = 0; /* upper addr */
-                *cs++ = 0; /* value */
-        } else  {
-                *cs++ = 0;
-                *cs++ = MI_NOOP;
-        }
-        intel_ring_advance(req, cs);
-        return 0;
-}
-
-static int
-gen8_emit_bb_start(struct drm_i915_gem_request *req,
-                   u64 offset, u32 len,
-                   unsigned int dispatch_flags)
-{
-        bool ppgtt = USES_PPGTT(req->i915) &&
-                        !(dispatch_flags & I915_DISPATCH_SECURE);
-        u32 *cs;
-
-        cs = intel_ring_begin(req, 4);
-        if (IS_ERR(cs))
-                return PTR_ERR(cs);
-
-        /* FIXME(BDW): Address space and security selectors. */
-        *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
-                I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
-        *cs++ = lower_32_bits(offset);
-        *cs++ = upper_32_bits(offset);
+        *cs++ = 0;
         *cs++ = MI_NOOP;
         intel_ring_advance(req, cs);
-
         return 0;
 }
 
@@ -1905,8 +1682,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
                 return PTR_ERR(cs);
 
         cmd = MI_FLUSH_DW;
-        if (INTEL_GEN(req->i915) >= 8)
-                cmd += 1;
 
         /* We always require a command barrier so that subsequent
          * commands, such as breadcrumb interrupts, are strictly ordered
@@ -1925,13 +1700,8 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
                 cmd |= MI_INVALIDATE_TLB;
         *cs++ = cmd;
         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
-        if (INTEL_GEN(req->i915) >= 8) {
-                *cs++ = 0; /* upper addr */
-                *cs++ = 0; /* value */
-        } else  {
-                *cs++ = 0;
-                *cs++ = MI_NOOP;
-        }
+        *cs++ = 0;
+        *cs++ = MI_NOOP;
         intel_ring_advance(req, cs);
 
         return 0;
@@ -1940,110 +1710,61 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
                                        struct intel_engine_cs *engine)
 {
-        struct drm_i915_gem_object *obj;
-        int ret, i;
+        int i;
 
         if (!i915_modparams.semaphores)
                 return;
 
-        if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
-                struct i915_vma *vma;
-
-                obj = i915_gem_object_create(dev_priv, PAGE_SIZE);
-                if (IS_ERR(obj))
-                        goto err;
-
-                vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
-                if (IS_ERR(vma))
-                        goto err_obj;
-
-                ret = i915_gem_object_set_to_gtt_domain(obj, false);
-                if (ret)
-                        goto err_obj;
-
-                ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
-                if (ret)
-                        goto err_obj;
+        GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
+        engine->semaphore.sync_to = gen6_ring_sync_to;
+        engine->semaphore.signal = gen6_signal;
 
-                dev_priv->semaphore = vma;
-        }
-
-        if (INTEL_GEN(dev_priv) >= 8) {
-                u32 offset = i915_ggtt_offset(dev_priv->semaphore);
-
-                engine->semaphore.sync_to = gen8_ring_sync_to;
-                engine->semaphore.signal = gen8_xcs_signal;
-
-                for (i = 0; i < I915_NUM_ENGINES; i++) {
-                        u32 ring_offset;
-
-                        if (i != engine->id)
-                                ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
-                        else
-                                ring_offset = MI_SEMAPHORE_SYNC_INVALID;
-
-                        engine->semaphore.signal_ggtt[i] = ring_offset;
-                }
-        } else if (INTEL_GEN(dev_priv) >= 6) {
-                engine->semaphore.sync_to = gen6_ring_sync_to;
-                engine->semaphore.signal = gen6_signal;
-
-                /*
-                 * The current semaphore is only applied on pre-gen8
-                 * platform.  And there is no VCS2 ring on the pre-gen8
-                 * platform. So the semaphore between RCS and VCS2 is
-                 * initialized as INVALID.  Gen8 will initialize the
-                 * sema between VCS2 and RCS later.
-                 */
-                for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
-                        static const struct {
-                                u32 wait_mbox;
-                                i915_reg_t mbox_reg;
-                        } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
-                                [RCS_HW] = {
-                                        [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
-                                        [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
-                                        [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
-                                },
-                                [VCS_HW] = {
-                                        [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
-                                        [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
-                                        [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
-                                },
-                                [BCS_HW] = {
-                                        [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
-                                        [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
-                                        [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
-                                },
-                                [VECS_HW] = {
-                                        [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
-                                        [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
-                                        [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
-                                },
-                        };
+        /*
+         * The current semaphore is only applied on pre-gen8
+         * platform.  And there is no VCS2 ring on the pre-gen8
+         * platform. So the semaphore between RCS and VCS2 is
+         * initialized as INVALID.
+         */
+        for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
+                static const struct {
                         u32 wait_mbox;
                         i915_reg_t mbox_reg;
+                } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
+                        [RCS_HW] = {
+                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
+                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
+                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
+                        },
+                        [VCS_HW] = {
+                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
+                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
+                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
+                        },
+                        [BCS_HW] = {
+                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
+                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
+                                [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
+                        },
+                        [VECS_HW] = {
+                                [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
+                                [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
+                                [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
+                        },
+                };
+                u32 wait_mbox;
+                i915_reg_t mbox_reg;
 
-                        if (i == engine->hw_id) {
-                                wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
-                                mbox_reg = GEN6_NOSYNC;
-                        } else {
-                                wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
-                                mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
-                        }
-
-                        engine->semaphore.mbox.wait[i] = wait_mbox;
-                        engine->semaphore.mbox.signal[i] = mbox_reg;
+                if (i == engine->hw_id) {
+                        wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
+                        mbox_reg = GEN6_NOSYNC;
+                } else {
+                        wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
+                        mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
                 }
-        }
-
-        return;
 
-err_obj:
-        i915_gem_object_put(obj);
-err:
-        DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
-        i915_modparams.semaphores = 0;
+                engine->semaphore.mbox.wait[i] = wait_mbox;
+                engine->semaphore.mbox.signal[i] = mbox_reg;
+        }
 }
 
 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
@@ -2051,11 +1772,7 @@ static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
 {
         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
 
-        if (INTEL_GEN(dev_priv) >= 8) {
-                engine->irq_enable = gen8_irq_enable;
-                engine->irq_disable = gen8_irq_disable;
-                engine->irq_seqno_barrier = gen6_seqno_barrier;
-        } else if (INTEL_GEN(dev_priv) >= 6) {
+        if (INTEL_GEN(dev_priv) >= 6) {
                 engine->irq_enable = gen6_irq_enable;
                 engine->irq_disable = gen6_irq_disable;
                 engine->irq_seqno_barrier = gen6_seqno_barrier;
@@ -2090,6 +1807,9 @@ static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
                                       struct intel_engine_cs *engine)
 {
+        /* gen8+ are only supported with execlists */
+        GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
+
         intel_ring_init_irq(dev_priv, engine);
         intel_ring_init_semaphores(dev_priv, engine);
 
@@ -2109,20 +1829,14 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
 
                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
-                if (INTEL_GEN(dev_priv) >= 8) {
-                        engine->emit_breadcrumb_sz += num_rings * 6;
-                } else {
-                        engine->emit_breadcrumb_sz += num_rings * 3;
-                        if (num_rings & 1)
-                                engine->emit_breadcrumb_sz++;
-                }
+                engine->emit_breadcrumb_sz += num_rings * 3;
+                if (num_rings & 1)
+                        engine->emit_breadcrumb_sz++;
         }
 
         engine->set_default_submission = i9xx_set_default_submission;
 
-        if (INTEL_GEN(dev_priv) >= 8)
-                engine->emit_bb_start = gen8_emit_bb_start;
-        else if (INTEL_GEN(dev_priv) >= 6)
+        if (INTEL_GEN(dev_priv) >= 6)
                 engine->emit_bb_start = gen6_emit_bb_start;
         else if (INTEL_GEN(dev_priv) >= 4)
                 engine->emit_bb_start = i965_emit_bb_start;
@@ -2142,20 +1856,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
         if (HAS_L3_DPF(dev_priv))
                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-        if (INTEL_GEN(dev_priv) >= 8) {
-                engine->init_context = intel_rcs_ctx_init;
-                engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
-                engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
-                engine->emit_flush = gen8_render_ring_flush;
-                if (i915_modparams.semaphores) {
-                        int num_rings;
-
-                        engine->semaphore.signal = gen8_rcs_signal;
-
-                        num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
-                        engine->emit_breadcrumb_sz += num_rings * 8;
-                }
-        } else if (INTEL_GEN(dev_priv) >= 6) {
+        if (INTEL_GEN(dev_priv) >= 6) {
                 engine->init_context = intel_rcs_ctx_init;
                 engine->emit_flush = gen7_render_ring_flush;
                 if (IS_GEN6(dev_priv))
@@ -2174,7 +1875,6 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
                 engine->emit_bb_start = hsw_emit_bb_start;
 
         engine->init_hw = init_render_ring;
-        engine->cleanup = render_ring_cleanup;
 
         ret = intel_init_ring_buffer(engine);
         if (ret)
@@ -2204,8 +1904,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
                 if (IS_GEN6(dev_priv))
                         engine->set_default_submission = gen6_bsd_set_default_submission;
                 engine->emit_flush = gen6_bsd_ring_flush;
-                if (INTEL_GEN(dev_priv) < 8)
-                        engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+                engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
         } else {
                 engine->mmio_base = BSD_RING_BASE;
                 engine->emit_flush = bsd_ring_flush;
@@ -2225,8 +1924,7 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
         intel_ring_default_vfuncs(dev_priv, engine);
 
         engine->emit_flush = gen6_ring_flush;
-        if (INTEL_GEN(dev_priv) < 8)
-                engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
+        engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
 
         return intel_init_ring_buffer(engine);
 }
@@ -2238,12 +1936,9 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
         intel_ring_default_vfuncs(dev_priv, engine);
 
         engine->emit_flush = gen6_ring_flush;
-
-        if (INTEL_GEN(dev_priv) < 8) {
-                engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
-                engine->irq_enable = hsw_vebox_irq_enable;
-                engine->irq_disable = hsw_vebox_irq_disable;
-        }
+        engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
+        engine->irq_enable = hsw_vebox_irq_enable;
+        engine->irq_disable = hsw_vebox_irq_disable;
 
         return intel_init_ring_buffer(engine);
 }