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authorChris Wilson <chris@chris-wilson.co.uk>2019-01-28 13:18:09 -0500
committerChris Wilson <chris@chris-wilson.co.uk>2019-01-28 14:07:02 -0500
commit52954edd1f7030f753a63093c16826ef50805098 (patch)
tree50290ce76648272e28736a7afb315e06357da1ba /drivers/gpu/drm/i915/intel_ringbuffer.c
parentb18fe4be59f215b1ce75f406d04810454f206faf (diff)
drm/i915: Allocate a status page for each timeline
Allocate a page for use as a status page by a group of timelines, as we only need a dword of storage for each (rounded up to the cacheline for safety) we can pack multiple timelines into the same page. Each timeline will then be able to track its own HW seqno. v2: Reuse the common per-engine HWSP for the solitary ringbuffer timeline, so that we do not have to emit (using per-gen specialised vfuncs) the breadcrumb into the distinct timeline HWSP and instead can keep on using the common MI_STORE_DWORD_INDEX. However, to maintain the sleight-of-hand for the global/per-context seqno switchover, we will store both temporarily (and so use a custom offset for the shared timeline HWSP until the switch over). v3: Keep things simple and allocate a page for each timeline, page sharing comes next. v4: I was caught repeating the same MI_STORE_DWORD_IMM over and over again in selftests. v5: And caught red handed copying create timeline + check. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190128181812.22804-3-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cb6d2aa2a829..174795622eb1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1545,9 +1545,13 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1545 struct intel_ring *ring; 1545 struct intel_ring *ring;
1546 int err; 1546 int err;
1547 1547
1548 intel_engine_setup_common(engine); 1548 err = intel_engine_setup_common(engine);
1549 if (err)
1550 return err;
1549 1551
1550 timeline = i915_timeline_create(engine->i915, engine->name); 1552 timeline = i915_timeline_create(engine->i915,
1553 engine->name,
1554 engine->status_page.vma);
1551 if (IS_ERR(timeline)) { 1555 if (IS_ERR(timeline)) {
1552 err = PTR_ERR(timeline); 1556 err = PTR_ERR(timeline);
1553 goto err; 1557 goto err;
@@ -1571,6 +1575,8 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1571 if (err) 1575 if (err)
1572 goto err_unpin; 1576 goto err_unpin;
1573 1577
1578 GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma);
1579
1574 return 0; 1580 return 0;
1575 1581
1576err_unpin: 1582err_unpin: