Merge tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-intel into drm-next

- final bits (again) for the rotation support (Sonika Jindal)
- support bl_power in the intel backlight (Jani)
- vdd handling improvements from Ville
- i830M fixes from Ville
- piles of prep work all over to make skl enabling just plug in (Damien, Sonika)
- rename DP training defines to reflect latest edp standards, this touches all
  drm drivers supporting DP (Sonika Jindal)
- cache edids during single detect cycle to avoid re-reading it for e.g. audio,
  from Chris
- move w/a for registers which are stored in the hw context to the context init
  code (Arun&Damien)
- edp panel power sequencer fixes, helps chv a lot (Ville)
- piles of other chv fixes all over
- much more paranoid pageflip handling with stall detection and better recovery
  from Chris
- small things all over, as usual

* tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-intel: (114 commits)
  drm/i915: Update DRIVER_DATE to 20140905
  drm/i915: Decouple the stuck pageflip on modeset
  drm/i915: Check for a stalled page flip after each vblank
  drm/i915: Introduce a for_each_plane() macro
  drm/i915: Rewrite ABS_DIFF() in a safer manner
  drm/i915: Add comments explaining the vdd on/off functions
  drm/i915: Move DP port disable to post_disable for pch platforms
  drm/i915: Enable DP port earlier
  drm/i915: Turn on panel power before doing aux transfers
  drm/i915: Be more careful when picking the initial power sequencer pipe
  drm/i915: Reset power sequencer pipe tracking when disp2d is off
  drm/i915: Track which port is using which pipe's power sequencer
  drm/i915: Fix edp vdd locking
  drm/i915: Reset the HEAD pointer for the ring after writing START
  drm/i915: Fix unsafe vma iteration in i915_drop_caches
  drm/i915: init sprites with univeral plane init function
  drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs
  drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code
  drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code
  drm/i915: Don't call gen8_fbc_sw_flush() on chv
  ...

1 files changed, 160 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3c7283d8f160..109de2eeb9a8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -444,7 +444,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
                         return ret;
         }
 
-        return gen8_emit_pipe_control(ring, flags, scratch_addr);
+        ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
+        if (ret)
+                return ret;
+
+        if (!invalidate_domains && flush_domains)
+                return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
+
+        return 0;
 }
 
 static void ring_write_tail(struct intel_engine_cs *ring,
@@ -556,6 +563,14 @@ static int init_ring_common(struct intel_engine_cs *ring)
          * also enforces ordering), otherwise the hw might lose the new ring
          * register values. */
         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
+
+        /* WaClearRingBufHeadRegAtInit:ctg,elk */
+        if (I915_READ_HEAD(ring))
+                DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
+                          ring->name, I915_READ_HEAD(ring));
+        I915_WRITE_HEAD(ring, 0);
+        (void)I915_READ_HEAD(ring);
+
         I915_WRITE_CTL(ring,
                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
                         | RING_VALID);
@@ -650,6 +665,146 @@ err:
         return ret;
 }
 
+static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
+                                       u32 addr, u32 value)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
+                return;
+
+        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+        intel_ring_emit(ring, addr);
+        intel_ring_emit(ring, value);
+
+        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
+        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
+        /* value is updated with the status of remaining bits of this
+         * register when it is read from debugfs file
+         */
+        dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
+        dev_priv->num_wa_regs++;
+
+        return;
+}
+
+static int bdw_init_workarounds(struct intel_engine_cs *ring)
+{
+        int ret;
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        /*
+         * workarounds applied in this fn are part of register state context,
+         * they need to be re-initialized followed by gpu reset, suspend/resume,
+         * module reload.
+         */
+        dev_priv->num_wa_regs = 0;
+        memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
+
+        /*
+         * update the number of dwords required based on the
+         * actual number of workarounds applied
+         */
+        ret = intel_ring_begin(ring, 24);
+        if (ret)
+                return ret;
+
+        /* WaDisablePartialInstShootdown:bdw */
+        /* WaDisableThreadStallDopClockGating:bdw */
+        /* FIXME: Unclear whether we really need this on production bdw. */
+        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
+                           _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
+                                             | STALL_DOP_GATING_DISABLE));
+
+        /* WaDisableDopClockGating:bdw May not be needed for production */
+        intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
+                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
+        /*
+         * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
+         * pre-production hardware
+         */
+        intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
+                           _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
+                                              | GEN8_SAMPLER_POWER_BYPASS_DIS));
+
+        intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
+                           _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
+
+        intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
+                           _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
+
+        /* Use Force Non-Coherent whenever executing a 3D context. This is a
+         * workaround for for a possible hang in the unlikely event a TLB
+         * invalidation occurs during a PSD flush.
+         */
+        intel_ring_emit_wa(ring, HDC_CHICKEN0,
+                           _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
+
+        /* Wa4x4STCOptimizationDisable:bdw */
+        intel_ring_emit_wa(ring, CACHE_MODE_1,
+                           _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
+
+        /*
+         * BSpec recommends 8x4 when MSAA is used,
+         * however in practice 16x4 seems fastest.
+         *
+         * Note that PS/WM thread counts depend on the WIZ hashing
+         * disable bit, which we don't touch here, but it's good
+         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
+         */
+        intel_ring_emit_wa(ring, GEN7_GT_MODE,
+                           GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+
+        intel_ring_advance(ring);
+
+        DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
+                         dev_priv->num_wa_regs);
+
+        return 0;
+}
+
+static int chv_init_workarounds(struct intel_engine_cs *ring)
+{
+        int ret;
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        /*
+         * workarounds applied in this fn are part of register state context,
+         * they need to be re-initialized followed by gpu reset, suspend/resume,
+         * module reload.
+         */
+        dev_priv->num_wa_regs = 0;
+        memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
+
+        ret = intel_ring_begin(ring, 12);
+        if (ret)
+                return ret;
+
+        /* WaDisablePartialInstShootdown:chv */
+        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
+                           _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
+
+        /* WaDisableThreadStallDopClockGating:chv */
+        intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
+                           _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
+
+        /* WaDisableDopClockGating:chv (pre-production hw) */
+        intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
+                           _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+
+        /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
+        intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
+                           _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+
+        intel_ring_advance(ring);
+
+        return 0;
+}
+
 static int init_render_ring(struct intel_engine_cs *ring)
 {
         struct drm_device *dev = ring->dev;
@@ -2148,6 +2303,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                                         dev_priv->semaphore_obj = obj;
                         }
                 }
+                if (IS_CHERRYVIEW(dev))
+                        ring->init_context = chv_init_workarounds;
+                else
+                        ring->init_context = bdw_init_workarounds;
                 ring->add_request = gen6_add_request;
                 ring->flush = gen8_render_ring_flush;
                 ring->irq_get = gen8_ring_get_irq;