drm/i915: Flush pipecontrol post-sync writes

In order to flush the results from in-batch pipecontrol writes (used for
example in glQuery) before declaring the batch complete (and so declaring
the query results coherent), we need to set the FlushEnable bit in our
flushing pipecontrol. The FlushEnable bit "waits until all previous
writes of immediate data from post-sync circles are complete before
executing the next command".

I get GPU hangs on byt without flushing these writes (running ue4).
piglit has examples where the flush is required for correct rendering.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6e6b8db996ef..61b451fbd09e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -347,6 +347,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
         if (flush_domains) {
                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_FLUSH_ENABLE;
         }
         if (invalidate_domains) {
                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -418,6 +419,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
         if (flush_domains) {
                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_FLUSH_ENABLE;
         }
         if (invalidate_domains) {
                 flags |= PIPE_CONTROL_TLB_INVALIDATE;