drm/i915: Actually write the correct bits to DPFC_CONTROL on CTG

We set up all the bits for DPFC_CONTROL but forgot to actually
write them to the register. Oops.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a7af5b4d3eb4..75aceaaace8e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -165,7 +165,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc)
         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 
         /* enable it... */
-        I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
+        I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 
         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 }