Merge branch 'topic/bxt-stage1' into drm-intel-next-queued

Separate topic branch for bxt didn't work out since we needed to
refactor the gmbus code a bit to make it look decent. So backmerge.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 31 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fc7e0c7545fd..a80bfd565ce4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -98,6 +98,26 @@ static void skl_init_clock_gating(struct drm_device *dev)
                            GEN8_LQSC_RO_PERF_DIS);
 }
 
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        gen9_init_clock_gating(dev);
+
+        /*
+         * FIXME:
+         * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
+         * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
+         */
+         /* WaDisableSDEUnitClockGating:bxt */
+        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
+                   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+
+        /* FIXME: apply on A0 only */
+        I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
+}
+
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2542,6 +2562,7 @@ static bool ilk_disable_lp_wm(struct drm_device *dev)
  */
 
 #define SKL_DDB_SIZE            896     /* in blocks */
+#define BXT_DDB_SIZE            512
 
 static void
 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
@@ -2560,7 +2581,10 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
                 return;
         }
 
-        ddb_size = SKL_DDB_SIZE;
+        if (IS_BROXTON(dev))
+                ddb_size = BXT_DDB_SIZE;
+        else
+                ddb_size = SKL_DDB_SIZE;
 
         ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
@@ -6570,7 +6594,12 @@ void intel_init_pm(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen >= 9) {
                 skl_setup_wm_latency(dev);
 
-                dev_priv->display.init_clock_gating = skl_init_clock_gating;
+                if (IS_BROXTON(dev))
+                        dev_priv->display.init_clock_gating =
+                                bxt_init_clock_gating;
+                else if (IS_SKYLAKE(dev))
+                        dev_priv->display.init_clock_gating =
+                                skl_init_clock_gating;
                 dev_priv->display.update_wm = skl_update_wm;
                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
         } else if (HAS_PCH_SPLIT(dev)) {