Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

So here's the Broadwell pull request. From a kernel driver pov there's
two areas with big changes in Broadwell:
- Completely new enumerated interrupt bits. On the plus side it now looks
  fairly unform and sane.
- Completely new pagetable layout.

To ensure minimal impact on existing platforms we've refactored both the
irq and low-level gtt handling code a lot in anticipation of the bdw push.
So now bdw enabling in these areas just plugs in a bunch of vfuncs.

Otherwise it's all fairly harmless adjusting of switch cases and
if-ladders to shovel bdw into the right blocks. So minimized impact on
existing platforms. I've also merged the bdw-stage1 branch into our
-nightly integration branch for the past week to make sure we don't break
anything.

Note that there's still quite a flurry or patches floating around, but
I've figured I'll push this out. I plan to keep the bdw fixes separate
from my usual -fixes stream so that you can reject them easily in case it
still looks like too much churn. Also, bdw is for now hidden behind the
preliminary hw enabling module option. So there's no real pressure to get
follow-up patches all into 3.13.

* tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
  drm/i915: Mask the vblank interrupt on bdw by default
  drm/i915: Wire up cpu fifo underrun reporting support for bdw
  drm/i915: Optimize gen8_enable|disable_vblank functions
  drm/i915: Wire up pipe CRC support for bdw
  drm/i915: Wire up PCH interrupts for bdw
  drm/i915: Wire up port A aux channel
  drm/i915: Fix up the bdw pipe interrupt enable lists
  drm/i915: Optimize pipe irq handling on bdw
  drm/i915/bdw: Take render error interrupt out of the mask
  drm/i915/bdw: Add BDW PCH check first
  drm/i915: Use hsw_crt_get_config on BDW
  drm/i915/bdw: Change dp aux timeout to 600us on DDIA
  drm/i915/bdw: Enable trickle feed on Broadwell
  drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPoints
  drm/i915/bdw: conservative SBE VUE cache mode
  drm/i915/bdw: Limit SDE poly depth FIFO to 2
  drm/i915/bdw: Sampler power bypass disable
  ddrm/i915/bdw: Disable centroid pixel perf optimization
  drm/i915/bdw: BWGTLB clock gate disable
  drm/i915/bdw: Implement edp PSR workarounds
  ...

1 files changed, 152 insertions, 12 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 09ac9e79830f..0a07d7c9cafc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2291,7 +2291,9 @@ static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
 
 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
 {
-        if (INTEL_INFO(dev)->gen >= 7)
+        if (INTEL_INFO(dev)->gen >= 8)
+                return 3072;
+        else if (INTEL_INFO(dev)->gen >= 7)
                 return 768;
         else
                 return 512;
@@ -2336,7 +2338,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
         }
 
         /* clamp to max that the registers can hold */
-        if (INTEL_INFO(dev)->gen >= 7)
+        if (INTEL_INFO(dev)->gen >= 8)
+                max = level == 0 ? 255 : 2047;
+        else if (INTEL_INFO(dev)->gen >= 7)
                 /* IVB/HSW primary/sprite plane watermarks */
                 max = level == 0 ? 127 : 1023;
         else if (!is_sprite)
@@ -2366,10 +2370,13 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
 }
 
 /* Calculate the maximum FBC watermark */
-static unsigned int ilk_fbc_wm_max(void)
+static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
 {
         /* max that registers can hold */
-        return 15;
+        if (INTEL_INFO(dev)->gen >= 8)
+                return 31;
+        else
+                return 15;
 }
 
 static void ilk_compute_wm_maximums(struct drm_device *dev,
@@ -2381,7 +2388,7 @@ static void ilk_compute_wm_maximums(struct drm_device *dev,
         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
         max->cur = ilk_cursor_wm_max(dev, level, config);
-        max->fbc = ilk_fbc_wm_max();
+        max->fbc = ilk_fbc_wm_max(dev);
 }
 
 static bool ilk_validate_wm_level(int level,
@@ -2722,10 +2729,18 @@ static void hsw_compute_wm_results(struct drm_device *dev,
                 if (!r->enable)
                         break;
 
-                results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
-                                                          r->fbc_val,
-                                                          r->pri_val,
-                                                          r->cur_val);
+                results->wm_lp[wm_lp - 1] = WM3_LP_EN |
+                        ((level * 2) << WM1_LP_LATENCY_SHIFT) |
+                        (r->pri_val << WM1_LP_SR_SHIFT) |
+                        r->cur_val;
+
+                if (INTEL_INFO(dev)->gen >= 8)
+                        results->wm_lp[wm_lp - 1] |=
+                                r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
+                else
+                        results->wm_lp[wm_lp - 1] |=
+                                r->fbc_val << WM1_LP_FBC_SHIFT;
+
                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
         }
 
@@ -3747,6 +3762,78 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
         I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
 }
 
+static void gen8_enable_rps(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_ring_buffer *ring;
+        uint32_t rc6_mask = 0, rp_state_cap;
+        int unused;
+
+        /* 1a: Software RC state - RC0 */
+        I915_WRITE(GEN6_RC_STATE, 0);
+
+        /* 1c & 1d: Get forcewake during program sequence. Although the driver
+         * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+        gen6_gt_force_wake_get(dev_priv);
+
+        /* 2a: Disable RC states. */
+        I915_WRITE(GEN6_RC_CONTROL, 0);
+
+        rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+
+        /* 2b: Program RC6 thresholds.*/
+        I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+        I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+        for_each_ring(ring, dev_priv, unused)
+                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+        I915_WRITE(GEN6_RC_SLEEP, 0);
+        I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+
+        /* 3: Enable RC6 */
+        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
+                rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
+        DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
+        I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
+                        GEN6_RC_CTL_EI_MODE(1) |
+                        rc6_mask);
+
+        /* 4 Program defaults and thresholds for RPS*/
+        I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
+        I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
+        /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
+        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
+
+        /* Docs recommend 900MHz, and 300 MHz respectively */
+        I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
+                   dev_priv->rps.max_delay << 24 |
+                   dev_priv->rps.min_delay << 16);
+
+        I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
+        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
+        I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
+        I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
+
+        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+        /* 5: Enable RPS */
+        I915_WRITE(GEN6_RP_CONTROL,
+                   GEN6_RP_MEDIA_TURBO |
+                   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+                   GEN6_RP_MEDIA_IS_GFX |
+                   GEN6_RP_ENABLE |
+                   GEN6_RP_UP_BUSY_AVG |
+                   GEN6_RP_DOWN_IDLE_AVG);
+
+        /* 6: Ring frequency + overclocking (our driver does this later */
+
+        gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
+
+        gen6_enable_rps_interrupts(dev);
+
+        gen6_gt_force_wake_put(dev_priv);
+}
+
 static void gen6_enable_rps(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3909,7 +3996,10 @@ void gen6_update_ring_freq(struct drm_device *dev)
                 int diff = dev_priv->rps.max_delay - gpu_freq;
                 unsigned int ia_freq = 0, ring_freq = 0;
 
-                if (IS_HASWELL(dev)) {
+                if (INTEL_INFO(dev)->gen >= 8) {
+                        /* max(2 * GT, DDR). NB: GT is 50MHz units */
+                        ring_freq = max(min_ring_freq, gpu_freq);
+                } else if (IS_HASWELL(dev)) {
                         ring_freq = mult_frac(gpu_freq, 5, 4);
                         ring_freq = max(min_ring_freq, ring_freq);
                         /* leave ia_freq as the default, chosen by cpufreq */
@@ -4873,6 +4963,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 
         if (IS_VALLEYVIEW(dev)) {
                 valleyview_enable_rps(dev);
+        } else if (IS_BROADWELL(dev)) {
+                gen8_enable_rps(dev);
+                gen6_update_ring_freq(dev);
         } else {
                 gen6_enable_rps(dev);
                 gen6_update_ring_freq(dev);
@@ -5181,6 +5274,50 @@ static void lpt_suspend_hw(struct drm_device *dev)
         }
 }
 
+static void gen8_init_clock_gating(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        enum pipe i;
+
+        I915_WRITE(WM3_LP_ILK, 0);
+        I915_WRITE(WM2_LP_ILK, 0);
+        I915_WRITE(WM1_LP_ILK, 0);
+
+        /* FIXME(BDW): Check all the w/a, some might only apply to
+         * pre-production hw. */
+
+        WARN(!i915_preliminary_hw_support,
+             "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
+        I915_WRITE(HALF_SLICE_CHICKEN3,
+                   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
+        I915_WRITE(HALF_SLICE_CHICKEN3,
+                   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
+        I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
+
+        I915_WRITE(_3D_CHICKEN3,
+                   _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
+
+        I915_WRITE(COMMON_SLICE_CHICKEN2,
+                   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
+
+        I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
+                   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
+
+        /* WaSwitchSolVfFArbitrationPriority */
+        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
+
+        /* WaPsrDPAMaskVBlankInSRD */
+        I915_WRITE(CHICKEN_PAR1_1,
+                   I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
+
+        /* WaPsrDPRSUnmaskVBlankInSRD */
+        for_each_pipe(i) {
+                I915_WRITE(CHICKEN_PIPESL_1(i),
+                           I915_READ(CHICKEN_PIPESL_1(i) |
+                                     DPRS_MASK_VBLANK_SRD));
+        }
+}
+
 static void haswell_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5511,7 +5648,9 @@ static bool is_always_on_power_domain(struct drm_device *dev,
 
         BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
 
-        if (IS_HASWELL(dev)) {
+        if (IS_BROADWELL(dev)) {
+                always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS;
+        } else if (IS_HASWELL(dev)) {
                 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
         } else {
                 WARN_ON(1);
@@ -5833,6 +5972,8 @@ void intel_init_pm(struct drm_device *dev)
                                 dev_priv->display.update_wm = NULL;
                         }
                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
+                } else if (INTEL_INFO(dev)->gen == 8) {
+                        dev_priv->display.init_clock_gating = gen8_init_clock_gating;
                 } else
                         dev_priv->display.update_wm = NULL;
         } else if (IS_VALLEYVIEW(dev)) {
@@ -5995,4 +6136,3 @@ void intel_pm_init(struct drm_device *dev)
         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
                           intel_gen6_powersave_work);
 }
-