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authorDamien Lespiau <damien.lespiau@intel.com>2012-10-04 13:49:24 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-08 05:18:14 -0400
commita9627b881680c4419c61e70f60e8f957d8ef225c (patch)
tree91dd5e553e2d5b918cf886fdbe3b3eb08a9d2de3 /drivers/gpu/drm/i915/intel_pm.c
parent62cb944fa24728d164497834e4181ba0d266b32b (diff)
drm/i915: Remove the WaDisableBackToBackFlipFix w/a for Haswell
This workaround is only valid for IVB and VLV and the write triggers an error on HSW. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanonI@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0dd2ca707d0a..eb757e5f2d87 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3474,10 +3474,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
3474 I915_WRITE(_3D_CHICKEN3, 3474 I915_WRITE(_3D_CHICKEN3,
3475 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3475 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3476 3476
3477 I915_WRITE(IVB_CHICKEN3,
3478 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3479 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3480
3481 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3477 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3482 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3478 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3483 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3479 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);