drm/i915: Separate RPS and RC6 handling for gen6+

This patch separates enable/disable of RC6 and RPS for gen6+
platforms prior to VLV.

v2: Fixed checkpatch issue. (Sagar)

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> #1
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1507360055-19948-2-git-send-email-sagar.a.kamble@intel.com
Acked-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010213010.7415-1-chris@chris-wilson.co.uk

1 files changed, 29 insertions, 14 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 39acfadb5a21..dfa9afe9cb61 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6334,9 +6334,13 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv)
         I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
-static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
 {
         I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
+static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+{
         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
         I915_WRITE(GEN6_RP_CONTROL, 0);
 }
@@ -6694,7 +6698,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static void gen6_enable_rps(struct drm_i915_private *dev_priv)
+static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
 {
         struct intel_engine_cs *engine;
         enum intel_engine_id id;
@@ -6705,12 +6709,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
 
         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
-        /* Here begins a magic sequence of register writes to enable
-         * auto-downclocking.
-         *
-         * Perhaps there might be some value in exposing these to
-         * userspace...
-         */
         I915_WRITE(GEN6_RC_STATE, 0);
 
         /* Clear the DBG now so we don't confuse earlier errors */
@@ -6764,12 +6762,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
                    GEN6_RC_CTL_EI_MODE(1) |
                    GEN6_RC_CTL_HW_ENABLE);
 
-        /* Power down if completely idle for over 50ms */
-        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
-        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
-
-        reset_rps(dev_priv, gen6_set_rps);
-
         rc6vids = 0;
         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
         if (IS_GEN6(dev_priv) && ret) {
@@ -6787,6 +6779,27 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
+static void gen6_enable_rps(struct drm_i915_private *dev_priv)
+{
+        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+        /* Here begins a magic sequence of register writes to enable
+         * auto-downclocking.
+         *
+         * Perhaps there might be some value in exposing these to
+         * userspace...
+         */
+        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+        /* Power down if completely idle for over 50ms */
+        I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
+        I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+        reset_rps(dev_priv, gen6_set_rps);
+
+        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 {
         int min_freq = 15;
@@ -7936,6 +7949,7 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
         } else if (IS_VALLEYVIEW(dev_priv)) {
                 valleyview_disable_rps(dev_priv);
         } else if (INTEL_GEN(dev_priv) >= 6) {
+                gen6_disable_rc6(dev_priv);
                 gen6_disable_rps(dev_priv);
         }  else if (IS_IRONLAKE_M(dev_priv)) {
                 ironlake_disable_drps(dev_priv);
@@ -7972,6 +7986,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
                 gen8_enable_rps(dev_priv);
                 gen6_update_ring_freq(dev_priv);
         } else if (INTEL_GEN(dev_priv) >= 6) {
+                gen6_enable_rc6(dev_priv);
                 gen6_enable_rps(dev_priv);
                 gen6_update_ring_freq(dev_priv);
         } else if (IS_IRONLAKE_M(dev_priv)) {