drm/i915: Colocate all GT access routines in the same file

Currently, the register access code is split between i915_drv.c and
intel_pm.c. It only bares a superficial resemblance to the reset of the
powermanagement code, so move it all into its own file. This is to ease
further patches to enforce serialised register access.

v2: Scan for random abuse of I915_WRITE_NOTRACE
v3: Take the opportunity to rename the GT functions as uncore. Uncore is
the term used by the hardware design (and bspec) for all functions
outside of the GPU (and CPU) cores in what is also known as the System
Agent.
v4: Rebase onto SNB rc6 fixes

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Wrestle patch into applying and inline
intel_uncore_early_sanitize (plus move the old comment to the new
function). Also keep the _santize postfix for intel_uncore_sanitize.]
[danvet: Squash in fixup spotted by Chris on irc: We need to call
intel_pm_init before intel_uncore_sanitize since the later will call
cancel_work on the delayed rps setup work the former initializes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 8 insertions, 250 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 74d6c4d78360..0a5ba92a4b12 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -32,8 +32,6 @@
 #include <linux/module.h>
 #include <drm/i915_powerwell.h>
 
-#define FORCEWAKE_ACK_TIMEOUT_MS 2
-
 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  * during in-memory transfers and, therefore, reduce the power packet.
@@ -5289,254 +5287,6 @@ void intel_init_pm(struct drm_device *dev)
         }
 }
 
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
-{
-        u32 gt_thread_status_mask;
-
-        if (IS_HASWELL(dev_priv->dev))
-                gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
-        else
-                gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
-
-        /* w/a for a sporadic read returning 0 by waiting for the GT
-         * thread to wake up.
-         */
-        if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
-                DRM_ERROR("GT thread status wait timed out\n");
-}
-
-static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE, 0);
-        POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
-}
-
-static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
-{
-        if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
-
-        I915_WRITE_NOTRACE(FORCEWAKE, 1);
-        POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
-
-        if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
-
-        /* WaRsForcewakeWaitTC0:snb */
-        __gen6_gt_wait_for_thread_c0(dev_priv);
-}
-
-static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
-        /* something from same cacheline, but !FORCEWAKE_MT */
-        POSTING_READ(ECOBUS);
-}
-
-static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
-{
-        u32 forcewake_ack;
-
-        if (IS_HASWELL(dev_priv->dev))
-                forcewake_ack = FORCEWAKE_ACK_HSW;
-        else
-                forcewake_ack = FORCEWAKE_MT_ACK;
-
-        if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
-
-        I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-        /* something from same cacheline, but !FORCEWAKE_MT */
-        POSTING_READ(ECOBUS);
-
-        if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
-
-        /* WaRsForcewakeWaitTC0:ivb,hsw */
-        __gen6_gt_wait_for_thread_c0(dev_priv);
-}
-
-/*
- * Generally this is called implicitly by the register read function. However,
- * if some sequence requires the GT to not power down then this function should
- * be called at the beginning of the sequence followed by a call to
- * gen6_gt_force_wake_put() at the end of the sequence.
- */
-void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
-{
-        unsigned long irqflags;
-
-        spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
-        if (dev_priv->forcewake_count++ == 0)
-                dev_priv->gt.force_wake_get(dev_priv);
-        spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
-}
-
-void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
-{
-        u32 gtfifodbg;
-        gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
-        if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
-             "MMIO read or write has been dropped %x\n", gtfifodbg))
-                I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
-}
-
-static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE, 0);
-        /* something from same cacheline, but !FORCEWAKE */
-        POSTING_READ(ECOBUS);
-        gen6_gt_check_fifodbg(dev_priv);
-}
-
-static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-        /* something from same cacheline, but !FORCEWAKE_MT */
-        POSTING_READ(ECOBUS);
-        gen6_gt_check_fifodbg(dev_priv);
-}
-
-/*
- * see gen6_gt_force_wake_get()
- */
-void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
-{
-        unsigned long irqflags;
-
-        spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
-        if (--dev_priv->forcewake_count == 0)
-                dev_priv->gt.force_wake_put(dev_priv);
-        spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
-}
-
-int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
-{
-        int ret = 0;
-
-        if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
-                int loop = 500;
-                u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
-                while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
-                        udelay(10);
-                        fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
-                }
-                if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
-                        ++ret;
-                dev_priv->gt_fifo_count = fifo;
-        }
-        dev_priv->gt_fifo_count--;
-
-        return ret;
-}
-
-static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
-        /* something from same cacheline, but !FORCEWAKE_VLV */
-        POSTING_READ(FORCEWAKE_ACK_VLV);
-}
-
-static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
-{
-        if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
-
-        I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-        I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
-                           _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
-
-        if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
-
-        if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
-                             FORCEWAKE_KERNEL),
-                            FORCEWAKE_ACK_TIMEOUT_MS))
-                DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
-
-        /* WaRsForcewakeWaitTC0:vlv */
-        __gen6_gt_wait_for_thread_c0(dev_priv);
-}
-
-static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
-{
-        I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-        I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
-                           _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
-        /* The below doubles as a POSTING_READ */
-        gen6_gt_check_fifodbg(dev_priv);
-}
-
-void intel_gt_sanitize(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        if (IS_VALLEYVIEW(dev)) {
-                vlv_force_wake_reset(dev_priv);
-        } else if (INTEL_INFO(dev)->gen >= 6) {
-                __gen6_gt_force_wake_reset(dev_priv);
-                if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
-                        __gen6_gt_force_wake_mt_reset(dev_priv);
-        }
-
-        /* BIOS often leaves RC6 enabled, but disable it for hw init */
-        if (INTEL_INFO(dev)->gen >= 6)
-                intel_disable_gt_powersave(dev);
-}
-
-void intel_gt_init(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        if (IS_VALLEYVIEW(dev)) {
-                dev_priv->gt.force_wake_get = vlv_force_wake_get;
-                dev_priv->gt.force_wake_put = vlv_force_wake_put;
-        } else if (IS_HASWELL(dev)) {
-                dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
-                dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
-        } else if (IS_IVYBRIDGE(dev)) {
-                u32 ecobus;
-
-                /* IVB configs may use multi-threaded forcewake */
-
-                /* A small trick here - if the bios hasn't configured
-                 * MT forcewake, and if the device is in RC6, then
-                 * force_wake_mt_get will not wake the device and the
-                 * ECOBUS read will return zero. Which will be
-                 * (correctly) interpreted by the test below as MT
-                 * forcewake being disabled.
-                 */
-                mutex_lock(&dev->struct_mutex);
-                __gen6_gt_force_wake_mt_get(dev_priv);
-                ecobus = I915_READ_NOTRACE(ECOBUS);
-                __gen6_gt_force_wake_mt_put(dev_priv);
-                mutex_unlock(&dev->struct_mutex);
-
-                if (ecobus & FORCEWAKE_MT_ENABLE) {
-                        dev_priv->gt.force_wake_get =
-                                                __gen6_gt_force_wake_mt_get;
-                        dev_priv->gt.force_wake_put =
-                                                __gen6_gt_force_wake_mt_put;
-                } else {
-                        DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
-                        DRM_INFO("when using vblank-synced partial screen updates.\n");
-                        dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
-                        dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
-                }
-        } else if (IS_GEN6(dev)) {
-                dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
-                dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
-        }
-        INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
-                          intel_gen6_powersave_work);
-}
-
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
 {
         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -5639,3 +5389,11 @@ int vlv_freq_opcode(int ddr_freq, int val)
         return val;
 }
 
+void intel_pm_init(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
+                          intel_gen6_powersave_work);
+}
+