drm/i915: Agressive downclocking on Baytrail

Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.

v2: Rebase
v3: Exclude Cherrytrail as Deepak was concerned that the increased
number of register writes would wake the common powerwell too often.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Deepak S <deepak.s@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67e1e61c50e7..9c705dec853e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3934,6 +3934,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
                     GEN6_RP_DOWN_IDLE_AVG);
 
         dev_priv->rps.power = new_power;
+        dev_priv->rps.up_threshold = threshold_up;
+        dev_priv->rps.down_threshold = threshold_down;
         dev_priv->rps.last_adj = 0;
 }
 
@@ -4005,8 +4007,11 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
                       "Odd GPU freq value\n"))
                 val &= ~1;
 
-        if (val != dev_priv->rps.cur_freq)
+        if (val != dev_priv->rps.cur_freq) {
                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+                if (!IS_CHERRYVIEW(dev_priv))
+                        gen6_set_rps_thresholds(dev_priv, val);
+        }
 
         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
 
@@ -4055,6 +4060,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
                                 & GENFREQSTATUS) == 0, 100))
                 DRM_ERROR("timed out waiting for Punit\n");
 
+        gen6_set_rps_thresholds(dev_priv, val);
         vlv_force_gfx_clock(dev_priv, false);
 
         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));