drm/i915/chv: Set soft reset override bit for data lane resets

The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.

v2: Fix mispalced ';' (Mika)

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9ea494a2a32e..f66c7a2ebd9a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1259,6 +1259,10 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Propagate soft reset to data lane reset */
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -1281,6 +1285,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Deassert soft data lane reset*/
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);