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authorDave Airlie <airlied@redhat.com>2016-07-14 23:50:58 -0400
committerDave Airlie <airlied@redhat.com>2016-07-14 23:50:58 -0400
commitff37c05a996bb96eccc21f4fb1b32ba0e24f3443 (patch)
treec09b09b37521f2f8f3f7a9bb3b0a33a2b3bde1a1 /drivers/gpu/drm/i915/intel_fifo_underrun.c
parent6c181c82106e12dced317e93a7a396cbb8c64f75 (diff)
parent0b2c0582f1570bfc95aa9ac1cd340a215d8e8335 (diff)
Merge tag 'drm-intel-next-2016-07-11' of git://anongit.freedesktop.org/drm-intel into drm-next
- select igt testing depencies for CONFIG_DRM_I915_DEBUG (Chris) - track outputs in crtc state and clean up all our ad-hoc connector/encoder walking in modest code (Ville) - demidlayer drm_device/drm_i915_private (Chris Wilson) - thundering herd fix from Chris Wilson, with lots of help from Tvrtko Ursulin - piles of assorted clean and fallout from the thundering herd fix - documentation and more tuning for waitboosting (Chris) - pooled EU support on bxt (Arun Siluvery) - bxt support is no longer considered prelimary! - ring/engine vfunc cleanup from Tvrtko - introduce intel_wait_for_register helper (Chris) - opregion updates (Jani Nukla) - tuning and fixes for wait_for macros (Tvrkto&Imre) - more kabylake pci ids (Rodrigo) - pps cleanup and fixes for bxt (Imre) - move sink crc support over to atomic state (Maarten) - fix up async fbdev init ordering (Chris) - fbc fixes from Paulo and Chris * tag 'drm-intel-next-2016-07-11' of git://anongit.freedesktop.org/drm-intel: (223 commits) drm/i915: Update DRIVER_DATE to 20160711 drm/i915: Select DRM_VGEM for igt drm/i915: Select X86_MSR for igt drm/i915: Fill unused GGTT with scratch pages for VT-d drm/i915: Introduce Kabypoint PCH for Kabylake H/DT. drm/i915:gen9: implement WaMediaPoolStateCmdInWABB drm/i915: Check for invalid cloning earlier during modeset drm/i915: Simplify hdmi_12bpc_possible() drm/i915: Kill has_dsi_encoder drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/ drm/i915: Replace some open coded intel_crtc_has_dp_encoder()s drm/i915: Kill has_dp_encoder from pipe_config drm/i915: Replace manual lvds and sdvo/hdmi counting with intel_crtc_has_type() drm/i915: Unify intel_pipe_has_type() and intel_pipe_will_have_type() drm/i915: Add output_types bitmask into the crtc state drm/i915: Remove encoder type checks from MST suspend/resume drm/i915: Don't mark eDP encoders as MST capable drm/i915: avoid wait_for_atomic() in non-atomic host2guc_action() drm/i915: Group the irq breadcrumb variables into the same cacheline drm/i915: Wake up the bottom-half if we steal their interrupt ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fifo_underrun.c')
-rw-r--r--drivers/gpu/drm/i915/intel_fifo_underrun.c30
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 9be839a242f9..2aa744081f09 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -50,7 +50,7 @@
50 50
51static bool ivb_can_enable_err_int(struct drm_device *dev) 51static bool ivb_can_enable_err_int(struct drm_device *dev)
52{ 52{
53 struct drm_i915_private *dev_priv = dev->dev_private; 53 struct drm_i915_private *dev_priv = to_i915(dev);
54 struct intel_crtc *crtc; 54 struct intel_crtc *crtc;
55 enum pipe pipe; 55 enum pipe pipe;
56 56
@@ -68,7 +68,7 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
68 68
69static bool cpt_can_enable_serr_int(struct drm_device *dev) 69static bool cpt_can_enable_serr_int(struct drm_device *dev)
70{ 70{
71 struct drm_i915_private *dev_priv = dev->dev_private; 71 struct drm_i915_private *dev_priv = to_i915(dev);
72 enum pipe pipe; 72 enum pipe pipe;
73 struct intel_crtc *crtc; 73 struct intel_crtc *crtc;
74 74
@@ -105,7 +105,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
105 enum pipe pipe, 105 enum pipe pipe,
106 bool enable, bool old) 106 bool enable, bool old)
107{ 107{
108 struct drm_i915_private *dev_priv = dev->dev_private; 108 struct drm_i915_private *dev_priv = to_i915(dev);
109 i915_reg_t reg = PIPESTAT(pipe); 109 i915_reg_t reg = PIPESTAT(pipe);
110 u32 pipestat = I915_READ(reg) & 0xffff0000; 110 u32 pipestat = I915_READ(reg) & 0xffff0000;
111 111
@@ -123,7 +123,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
123static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 123static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
124 enum pipe pipe, bool enable) 124 enum pipe pipe, bool enable)
125{ 125{
126 struct drm_i915_private *dev_priv = dev->dev_private; 126 struct drm_i915_private *dev_priv = to_i915(dev);
127 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 127 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
128 DE_PIPEB_FIFO_UNDERRUN; 128 DE_PIPEB_FIFO_UNDERRUN;
129 129
@@ -154,7 +154,7 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
154 enum pipe pipe, 154 enum pipe pipe,
155 bool enable, bool old) 155 bool enable, bool old)
156{ 156{
157 struct drm_i915_private *dev_priv = dev->dev_private; 157 struct drm_i915_private *dev_priv = to_i915(dev);
158 if (enable) { 158 if (enable) {
159 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 159 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
160 160
@@ -176,7 +176,7 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
176static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 176static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
177 enum pipe pipe, bool enable) 177 enum pipe pipe, bool enable)
178{ 178{
179 struct drm_i915_private *dev_priv = dev->dev_private; 179 struct drm_i915_private *dev_priv = to_i915(dev);
180 180
181 if (enable) 181 if (enable)
182 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); 182 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
@@ -188,7 +188,7 @@ static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
188 enum transcoder pch_transcoder, 188 enum transcoder pch_transcoder,
189 bool enable) 189 bool enable)
190{ 190{
191 struct drm_i915_private *dev_priv = dev->dev_private; 191 struct drm_i915_private *dev_priv = to_i915(dev);
192 uint32_t bit = (pch_transcoder == TRANSCODER_A) ? 192 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
193 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 193 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
194 194
@@ -220,7 +220,7 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
220 enum transcoder pch_transcoder, 220 enum transcoder pch_transcoder,
221 bool enable, bool old) 221 bool enable, bool old)
222{ 222{
223 struct drm_i915_private *dev_priv = dev->dev_private; 223 struct drm_i915_private *dev_priv = to_i915(dev);
224 224
225 if (enable) { 225 if (enable) {
226 I915_WRITE(SERR_INT, 226 I915_WRITE(SERR_INT,
@@ -244,7 +244,7 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
244static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 244static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
245 enum pipe pipe, bool enable) 245 enum pipe pipe, bool enable)
246{ 246{
247 struct drm_i915_private *dev_priv = dev->dev_private; 247 struct drm_i915_private *dev_priv = to_i915(dev);
248 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 248 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
250 bool old; 250 bool old;
@@ -289,7 +289,7 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
289 bool ret; 289 bool ret;
290 290
291 spin_lock_irqsave(&dev_priv->irq_lock, flags); 291 spin_lock_irqsave(&dev_priv->irq_lock, flags);
292 ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe, 292 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
293 enable); 293 enable);
294 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 294 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
295 295
@@ -334,10 +334,12 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
334 intel_crtc->pch_fifo_underrun_disabled = !enable; 334 intel_crtc->pch_fifo_underrun_disabled = !enable;
335 335
336 if (HAS_PCH_IBX(dev_priv)) 336 if (HAS_PCH_IBX(dev_priv))
337 ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, 337 ibx_set_fifo_underrun_reporting(&dev_priv->drm,
338 pch_transcoder,
338 enable); 339 enable);
339 else 340 else
340 cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder, 341 cpt_set_fifo_underrun_reporting(&dev_priv->drm,
342 pch_transcoder,
341 enable, old); 343 enable, old);
342 344
343 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 345 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -405,7 +407,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
405 407
406 spin_lock_irq(&dev_priv->irq_lock); 408 spin_lock_irq(&dev_priv->irq_lock);
407 409
408 for_each_intel_crtc(dev_priv->dev, crtc) { 410 for_each_intel_crtc(&dev_priv->drm, crtc) {
409 if (crtc->cpu_fifo_underrun_disabled) 411 if (crtc->cpu_fifo_underrun_disabled)
410 continue; 412 continue;
411 413
@@ -432,7 +434,7 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
432 434
433 spin_lock_irq(&dev_priv->irq_lock); 435 spin_lock_irq(&dev_priv->irq_lock);
434 436
435 for_each_intel_crtc(dev_priv->dev, crtc) { 437 for_each_intel_crtc(&dev_priv->drm, crtc) {
436 if (crtc->pch_fifo_underrun_disabled) 438 if (crtc->pch_fifo_underrun_disabled)
437 continue; 439 continue;
438 440