drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.

References: HSD#1937670

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230723.20898-1-rodrigo.vivi@intel.com

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a6ac9d0a4156..4b9b7828802d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
         /* WaPushConstantDereferenceHoldDisable:cnl */
         WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
 
+        /* FtrEnableFastAnisoL1BankingFix: cnl */
+        WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+
         /* WaEnablePreemptionGranularityControlByUMD:cnl */
         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
         if (ret)