diff options
author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2017-09-22 08:43:04 -0400 |
---|---|---|
committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2017-09-25 04:33:32 -0400 |
commit | 19df9a5782f51c900a730dae11e4abf85a0e5ebc (patch) | |
tree | 57f20b282b1eb4d612acc394e34e76e232b7eddb /drivers/gpu/drm/i915/intel_engine_cs.c | |
parent | b620e870218ebe75b8221c7596b46e36d8329c85 (diff) |
drm/i915: Move execlist initialization into intel_engine_cs.c
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.
v2: rebase with csb changes
v3: rebase
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20170922124307.10914-2-mika.kuoppala@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_engine_cs.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_engine_cs.c | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index bf132266a007..30035e59a784 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c | |||
@@ -382,6 +382,33 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) | |||
382 | engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id]; | 382 | engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id]; |
383 | } | 383 | } |
384 | 384 | ||
385 | static bool csb_force_mmio(struct drm_i915_private *i915) | ||
386 | { | ||
387 | /* GVT emulation depends upon intercepting CSB mmio */ | ||
388 | if (intel_vgpu_active(i915)) | ||
389 | return true; | ||
390 | |||
391 | /* | ||
392 | * IOMMU adds unpredictable latency causing the CSB write (from the | ||
393 | * GPU into the HWSP) to only be visible some time after the interrupt | ||
394 | * (missed breadcrumb syndrome). | ||
395 | */ | ||
396 | if (intel_vtd_active()) | ||
397 | return true; | ||
398 | |||
399 | return false; | ||
400 | } | ||
401 | |||
402 | static void intel_engine_init_execlist(struct intel_engine_cs *engine) | ||
403 | { | ||
404 | struct intel_engine_execlists * const execlists = &engine->execlists; | ||
405 | |||
406 | execlists->csb_use_mmio = csb_force_mmio(engine->i915); | ||
407 | |||
408 | execlists->queue = RB_ROOT; | ||
409 | execlists->first = NULL; | ||
410 | } | ||
411 | |||
385 | /** | 412 | /** |
386 | * intel_engines_setup_common - setup engine state not requiring hw access | 413 | * intel_engines_setup_common - setup engine state not requiring hw access |
387 | * @engine: Engine to setup. | 414 | * @engine: Engine to setup. |
@@ -393,8 +420,7 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine) | |||
393 | */ | 420 | */ |
394 | void intel_engine_setup_common(struct intel_engine_cs *engine) | 421 | void intel_engine_setup_common(struct intel_engine_cs *engine) |
395 | { | 422 | { |
396 | engine->execlists.queue = RB_ROOT; | 423 | intel_engine_init_execlist(engine); |
397 | engine->execlists.first = NULL; | ||
398 | 424 | ||
399 | intel_engine_init_timeline(engine); | 425 | intel_engine_init_timeline(engine); |
400 | intel_engine_init_hangcheck(engine); | 426 | intel_engine_init_hangcheck(engine); |