drm/i915: Apply OCD to VLV/CHV DPLL defines

Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5381ddcc2a79..f4438eb5b458 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -413,12 +413,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
         /* Disable DPOunit clock gating, can stall pipe
          * and we need DPLL REFA always enabled */
         tmp = I915_READ(DPLL(pipe));
-        tmp |= DPLL_REFA_CLK_ENABLE_VLV;
+        tmp |= DPLL_REF_CLK_ENABLE_VLV;
         I915_WRITE(DPLL(pipe), tmp);
 
         /* update the hw state for DPLL */
-        intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
-                DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+        intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
+                DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 
         tmp = I915_READ(DSPCLK_GATE_D);
         tmp |= DPOUNIT_CLOCK_GATE_DISABLE;