drm/i915/dsi: start using enum mipi_dsi_pixel_format

A small step moving us closer to DRM MIPI DSI code. Use enum
mipi_dsi_pixel_format instead of our own. The first benefit is being
able to use common mipi_dsi_pixel_format_to_bpp().

There's a little back and forth conversion with the VBT -> enum ->
register, since we have just shoved the VBT value into the register
directly. Longer term, all the VBT parsing and deciphering should be
done in intel_bios.c, and abstracted there.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458123700-16003-2-git-send-email-jani.nikula@intel.com

1 files changed, 20 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 01b8e9f4c272..ea78b0bf7e14 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -787,7 +787,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
         enum port port;
-        unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
+        unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
         unsigned int lane_count = intel_dsi->lane_count;
 
         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
@@ -849,6 +849,23 @@ static void set_dsi_timings(struct drm_encoder *encoder,
         }
 }
 
+static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
+{
+        switch (fmt) {
+        case MIPI_DSI_FMT_RGB888:
+                return VID_MODE_FORMAT_RGB888;
+        case MIPI_DSI_FMT_RGB666:
+                return VID_MODE_FORMAT_RGB666;
+        case MIPI_DSI_FMT_RGB666_PACKED:
+                return VID_MODE_FORMAT_RGB666_PACKED;
+        case MIPI_DSI_FMT_RGB565:
+                return VID_MODE_FORMAT_RGB565;
+        default:
+                MISSING_CASE(fmt);
+                return VID_MODE_FORMAT_RGB666;
+        }
+}
+
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 {
         struct drm_encoder *encoder = &intel_encoder->base;
@@ -858,7 +875,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
         enum port port;
-        unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
+        unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
         u32 val, tmp;
         u16 mode_hdisplay;
 
@@ -917,9 +934,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
         } else {
                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
-
-                /* XXX: cross-check bpp vs. pixel format? */
-                val |= intel_dsi->pixel_format;
+                val |= pixel_format_to_reg(intel_dsi->pixel_format);
         }
 
         tmp = 0;