Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Higlights here goes to many PSR fixes and improvements; to the Ice lake work with
power well support and begin of DSI support addition. Also there were many improvements
on execlists and interrupts for minimal latency on command submission; and many fixes
on selftests, mostly caught by our CI.

General driver:
- Clean-up on aux irq (Lucas)
- Mark expected switch fall-through for dealing with static analysis tools (Gustavo)

Gem:
- Different fixes for GuC (Chris, Anusha, Michal)
- Avoid self-relocation BIAS if no relocation (Chris)
- Improve debugging cases in on EINVAL return and vma allocation (Chris)
- Fixes and improvements on context destroying and freeing (Chris)
- Wait for engines to idle before retiring (Chris)
- Many improvements on execlists and interrupts for minimal latency on command submission (Chris)
- Many fixes in selftests, specially on cases highlighted on CI (Chris)
- Other fixes and improvements around GGTT (Chris)
- Prevent background reaping of active objects (Chris)

Display:
- Parallel modeset cleanup to fix driver reset (Chris)
- Get AUX power domain for DP main link (Imre)
- Clean-up on PSR unused func pointers (Rodrigo)
- Many PSR/PSR2 fixes and improvements (DK, Jose, Tarun)
- Add a PSR1 live status (Vathsala)
- Replace old drm_*_{un/reference} with put,get functions (Thomas)
- FBC fixes (Maarten)
- Abstract and document the usage of picking macros (Jani)
- Remove unnecessary check for unsupported modifiers for NV12. (DK)
- Interrupt fixes for display (Ville)
- Clean up on sdvo code (Ville)
- Clean up on current DSI code (Jani)
- Remove support for legacy debugfs crc interface (Maarten)
- Simplify get_encoder_power_domains (Imre)

Icelake:
- MG PLL fixes (Imre)
- Add hw workaround for alpha blending (Vandita)
- Add power well support (Imre)
- Add Interrupt Support (Anusha)
- Start to add support for DSI on Ice Lake (Madhav)

Signed-off-by: Dave Airlie <airlied@redhat.com>

# gpg: Signature made Tue 10 Jul 2018 08:41:37 AM AEST
# gpg:                using RSA key FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>"
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA
Link: https://patchwork.freedesktop.org/patch/msgid/20180710234349.GA16562@intel.com

1 files changed, 85 insertions, 24 deletions

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 156f8e4cbe4c..b51ad2917dbe 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2566,6 +2566,7 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
         switch (index) {
         default:
                 MISSING_CASE(index);
+                /* fall through */
         case 0:
                 link_clock = 540000;
                 break;
@@ -2639,6 +2640,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
                         switch (div1) {
                         default:
                                 MISSING_CASE(div1);
+                                /* fall through */
                         case 2:
                                 hsdiv = 0;
                                 break;
@@ -2812,25 +2814,31 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
                                 MG_PLL_SSC_FLLEN |
                                 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
 
-        pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART;
-
-        if (refclk_khz != 38400) {
-                pll_state->mg_pll_tdc_coldst_bias |=
-                        MG_PLL_TDC_COLDST_IREFINT_EN |
-                        MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
-                        MG_PLL_TDC_COLDST_COLDSTART |
-                        MG_PLL_TDC_TDCOVCCORR_EN |
-                        MG_PLL_TDC_TDCSEL(3);
-
-                pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
-                                         MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
-                                         MG_PLL_BIAS_BIAS_BONUS(10) |
-                                         MG_PLL_BIAS_BIASCAL_EN |
-                                         MG_PLL_BIAS_CTRIM(12) |
-                                         MG_PLL_BIAS_VREF_RDAC(4) |
-                                         MG_PLL_BIAS_IREFTRIM(iref_trim);
+        pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
+                                            MG_PLL_TDC_COLDST_IREFINT_EN |
+                                            MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
+                                            MG_PLL_TDC_TDCOVCCORR_EN |
+                                            MG_PLL_TDC_TDCSEL(3);
+
+        pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
+                                 MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
+                                 MG_PLL_BIAS_BIAS_BONUS(10) |
+                                 MG_PLL_BIAS_BIASCAL_EN |
+                                 MG_PLL_BIAS_CTRIM(12) |
+                                 MG_PLL_BIAS_VREF_RDAC(4) |
+                                 MG_PLL_BIAS_IREFTRIM(iref_trim);
+
+        if (refclk_khz == 38400) {
+                pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
+                pll_state->mg_pll_bias_mask = 0;
+        } else {
+                pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
+                pll_state->mg_pll_bias_mask = -1U;
         }
 
+        pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
+        pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+
         return true;
 }
 
@@ -2897,6 +2905,7 @@ static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
         switch (id) {
         default:
                 MISSING_CASE(id);
+                /* fall through */
         case DPLL_ID_ICL_DPLL0:
         case DPLL_ID_ICL_DPLL1:
                 return CNL_DPLL_ENABLE(id);
@@ -2939,18 +2948,41 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
         case DPLL_ID_ICL_MGPLL4:
                 port = icl_mg_pll_id_to_port(id);
                 hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
+                hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
                 hw_state->mg_clktop2_coreclkctl1 =
                         I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
+                hw_state->mg_clktop2_coreclkctl1 &=
+                        MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
                 hw_state->mg_clktop2_hsclkctl =
                         I915_READ(MG_CLKTOP2_HSCLKCTL(port));
+                hw_state->mg_clktop2_hsclkctl &=
+                        MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+                        MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+                        MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+                        MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
+
                 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
                 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(port));
                 hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
                 hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
                 hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
+
                 hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
                 hw_state->mg_pll_tdc_coldst_bias =
                         I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
+
+                if (dev_priv->cdclk.hw.ref == 38400) {
+                        hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
+                        hw_state->mg_pll_bias_mask = 0;
+                } else {
+                        hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
+                        hw_state->mg_pll_bias_mask = -1U;
+                }
+
+                hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
+                hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
                 break;
         default:
                 MISSING_CASE(id);
@@ -2978,19 +3010,48 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
 {
         struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
         enum port port = icl_mg_pll_id_to_port(pll->info->id);
+        u32 val;
+
+        /*
+         * Some of the following registers have reserved fields, so program
+         * these with RMW based on a mask. The mask can be fixed or generated
+         * during the calc/readout phase if the mask depends on some other HW
+         * state like refclk, see icl_calc_mg_pll_state().
+         */
+        val = I915_READ(MG_REFCLKIN_CTL(port));
+        val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+        val |= hw_state->mg_refclkin_ctl;
+        I915_WRITE(MG_REFCLKIN_CTL(port), val);
+
+        val = I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
+        val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+        val |= hw_state->mg_clktop2_coreclkctl1;
+        I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port), val);
+
+        val = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
+        val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+                 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
+                 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
+                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
+        val |= hw_state->mg_clktop2_hsclkctl;
+        I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), val);
 
-        I915_WRITE(MG_REFCLKIN_CTL(port), hw_state->mg_refclkin_ctl);
-        I915_WRITE(MG_CLKTOP2_CORECLKCTL1(port),
-                   hw_state->mg_clktop2_coreclkctl1);
-        I915_WRITE(MG_CLKTOP2_HSCLKCTL(port), hw_state->mg_clktop2_hsclkctl);
         I915_WRITE(MG_PLL_DIV0(port), hw_state->mg_pll_div0);
         I915_WRITE(MG_PLL_DIV1(port), hw_state->mg_pll_div1);
         I915_WRITE(MG_PLL_LF(port), hw_state->mg_pll_lf);
         I915_WRITE(MG_PLL_FRAC_LOCK(port), hw_state->mg_pll_frac_lock);
         I915_WRITE(MG_PLL_SSC(port), hw_state->mg_pll_ssc);
-        I915_WRITE(MG_PLL_BIAS(port), hw_state->mg_pll_bias);
-        I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port),
-                   hw_state->mg_pll_tdc_coldst_bias);
+
+        val = I915_READ(MG_PLL_BIAS(port));
+        val &= ~hw_state->mg_pll_bias_mask;
+        val |= hw_state->mg_pll_bias;
+        I915_WRITE(MG_PLL_BIAS(port), val);
+
+        val = I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
+        val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
+        val |= hw_state->mg_pll_tdc_coldst_bias;
+        I915_WRITE(MG_PLL_TDC_COLDST_BIAS(port), val);
+
         POSTING_READ(MG_PLL_TDC_COLDST_BIAS(port));
 }