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authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2018-10-04 05:46:03 -0400
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2018-10-05 09:19:08 -0400
commit958bb4528d16d0f6cdab7a34a9bd141b42768ca2 (patch)
treebc3cd668aaf850e3479efdf3a0c9fa9af67f2df7 /drivers/gpu/drm/i915/intel_dpio_phy.c
parentf56f6648404b411b377a3082bc9459fed66a968f (diff)
drm/i915: Get rid of crtc->config in chv_data_lane_soft_reset
Fixing chv_set_phy_signal_level() still requires too many levels of indirection to pass crtc_state along, but chv_data_lane_soft_reset() already has a crtc_state we can use. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181004094604.2646-13-maarten.lankhorst@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpio_phy.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dpio_phy.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 00b3ab656b06..3c7f10d17658 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -748,7 +748,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
748 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 748 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
749 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 749 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
750 750
751 if (crtc->config->lane_count > 2) { 751 if (crtc_state->lane_count > 2) {
752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
753 if (reset) 753 if (reset)
754 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 754 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
@@ -765,7 +765,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
765 val |= DPIO_PCS_CLK_SOFT_RESET; 765 val |= DPIO_PCS_CLK_SOFT_RESET;
766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
767 767
768 if (crtc->config->lane_count > 2) { 768 if (crtc_state->lane_count > 2) {
769 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 769 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
770 val |= CHV_PCS_REQ_SOFTRESET_EN; 770 val |= CHV_PCS_REQ_SOFTRESET_EN;
771 if (reset) 771 if (reset)